#include "types.h"
#include "arm9/ndma.h"
#include "arm9/interrupt.h"
#include "io.h"



void initHardware(void)
{
	// Enable all interrupts but these
	REG_IRQ_IE = ~(u32)(INTERRUPT_SDIO_1 | INTERRUPT_SDIO_1_ASYNC | INTERRUPT_SDIO_3 |
					INTERRUPT_SDIO_3_ASYNC | INTERRUPT_DEBUG_RECV | INTERRUPT_DEBUG_SEND |
					INTERRUPT_CTR_CARD_2 | INTERRUPT_CGC | INTERRUPT_CGC_DET |
					INTERRUPT_DMAC_2 | INTERRUPT_DMAC_2_ABORT);

	// Reserve DMA channel 0 and 1 for AES
	REG_NDMA0_SRC_ADDR = 0;
	REG_NDMA0_DST_ADDR = (u32)REG_AESWRFIFO;
	REG_NDMA0_WRITE_CNT = 4;
	REG_NDMA0_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
	REG_NDMA0_CNT = NDMA_REPEATING_MODE | NDMA_BLK_TRANS_WORD_COUNT(2) | NDMA_STARTUP_AES_IN |
					NDMA_SRC_UPDATE_INC | NDMA_DST_UPDATE_FIXED;

	REG_NDMA1_SRC_ADDR = (u32)REG_AESRDFIFO;
	REG_NDMA1_DST_ADDR = 0;
	REG_NDMA1_WRITE_CNT = 4;
	REG_NDMA1_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
	REG_NDMA1_CNT = NDMA_REPEATING_MODE | NDMA_BLK_TRANS_WORD_COUNT(2) | NDMA_STARTUP_AES_OUT |
					NDMA_SRC_UPDATE_FIXED | NDMA_DST_UPDATE_INC;
}