Rework sdmmc clocking configuration ...

Use 204 MHz as host clock in SDR104 mode instead of 136 MHz.
Due to this, also change the frequency init divider so the
initialization frequency is below 400 kHz.
This makes the clocks for SDMMC1 in all modes to match the TRM table.

Make it clear in the code that HS200/HS400 modes in fact use PLLP_OUT0
and not PLLC4_OUT2_LJ like the comment suggest. In fact selecting the
PLLC4_OUT2_LJ as clock source results in freeze after switching to
HS200/HS400 mode. This is most likely related to the PLLC4 not being
enabled, but it should be checked later.

Set the HS200/HS400 divider to 3, as this is what the code really did
set prior to this change - so this commit does not change that.

Configure Legacy 12 MHz clock to run at 12 MHz using the SW default
configuration (as per TRM) for the SDMMC legacy timer.

Introduce initial version of sdmmc_host_clock_delay() in order to use it
in places where the wait is host clock dependent. The way it is
implemented now does not change the sleep that was used instead.

fusee: Run periodic autocal only on the uSD controller (#137)

Merge pull request #132 from tslater2006/master ...

Add sdmmc_dump_regs function

Fix race conditions and misconfiguration in sdmmc ...

Properly configure pull up and pull down offsets for autocal.
Run autocal prior to every transfer.

Prevent race conditions in sdmmc_wait_for_event() - make sure the fault
handler has highest priority, then the target irq, state conditions and
finally the error mask.

Do not clear all bits (|=) when acknowledging fault conditions,
only acknowledge the fault conditions itself.

Enable interrupts before preparing command registers - if sdmmc is fast
enough it can actually finish transfer before we enabled the interrupts.
Enabling interrupts clears the COMMAND COMPLETE status bit.

Temporarily print all the sdmmc messages in stage2 - for yet unknown
reason respecting the log level results in some failures.

This results in working microsd card in stage2 on my switch with Samsung
EVO+ 256GB microsd card.

Switched to mmc_debug, and use inttypes

Add sdmmc_dump_regs function

Make sdmmc autocalibration follow TRM procedure ...

Sleep for 1 us, not 1 ms.
Timeout after 10 ms, set driver strength code values according to TRM.

Fix typo (mS) - time is in milliseconds, not milliSiemens.

Pass screen status and mmc struct from stage1 to 2

Set SDMMC controller to SDR104 as a workaround ...

According to Tegra X1 Series Processors Silicon Errata there is possible
misalignment of received data which results in a CRC error. The issue is
present only in SDR50 mode.

Refactor fusee's makefile

Fix mmc->allow_voltage_switching assignment in sdmmc_init

Copy latest sdmmc driver to stage2

fusee: work around some dual-init SDMMC issues

Stage1: fix SE issue too

Use uintX_t for the SE & copy bugfixed SE struct definition

Stage1: fix potential alignment issue

fusee: improve SDR104 frequency and support AUTOCMD23

Stage2: Add exception handlers

Fix stack overflow when chainloading stage2

Fix exception handlers (thanks @fincs)

[stage1] Add exception handlers... which somehow don't work?

Fusee use CAR reboot for fatal errors

Remove packed when not needed

wtf pmc reboot doesn't fully work -- display doesn't reinitialize

Introduce fatal_error

fusee: correct computation of tuning block size

fusee: begin adding support for MMC HS modes

fusee: SD: implement tuning, allowing for all SD UHS-I speed

fusee: SD driver: implement everything necessary for UHS except tuning

fusee: correct constants in CAR