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Set SDMMC controller to SDR104 as a workaround
According to Tegra X1 Series Processors Silicon Errata there is possible
misalignment of received data which results in a CRC error. The issue is
present only in SDR50 mode.
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1 parent c9723d7 commit 0534e36cf88716c113233f0cfe876e82f6654964
@Tomasz Moń Tomasz Moń authored on 27 May 2018
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fusee/fusee-primary/src/sdmmc.c
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fusee/fusee-secondary/src/sdmmc.c