diff --git a/include/arm11/start.h b/include/arm11/start.h
index 606c496..a5e4ca9 100644
--- a/include/arm11/start.h
+++ b/include/arm11/start.h
@@ -27,7 +27,7 @@
 {
 #endif
 
-void _start(void);
+noreturn void _start(void);
 void clearMem(u32 *adr, u32 size);
 void deinitCpu(void);
 
diff --git a/source/arm11/hardware/cpu.c b/source/arm11/hardware/cpu.c
index c50aa75..52ccaeb 100644
--- a/source/arm11/hardware/cpu.c
+++ b/source/arm11/hardware/cpu.c
@@ -26,7 +26,6 @@
 #include "arm11/hardware/scu.h"
 
 
-
 #ifdef CORE123_INIT
 static void NAKED core23Entry(void)
 {
@@ -50,9 +49,11 @@
 	// Jump to real entrypoint
 	_start();
 }
+#endif
 
 void core123Init(void)
 {
+#ifdef CORE123_INIT
 	if(REG_CFG11_SOCINFO & 2)
 	{
 		REG_CPU_II_CNT = 1;
@@ -122,8 +123,11 @@
 	// Wakeup core 1
 	*((vu32*)0x1FFFFFDC) = (u32)_start;  // Core 1 entrypoint
 	IRQ_softwareInterrupt(1, 0b0010);
-}
+#else
+	// Just enables the New 3DS FCRAM extension
+	if(REG_CFG11_SOCINFO & 2) CPU_setClock(1);
 #endif
+}
 
 void CPU_setClock(u16 clk)
 {
diff --git a/source/arm11/start.s b/source/arm11/start.s
index f98dba5..95a41dd 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -134,9 +134,7 @@
 	ldr r1, =fake_heap_end
 	str r0, [r1]
 	blx __libc_init_array       @ Initialize ctors and dtors
-#ifdef CORE123_INIT
 	blx core123Init
-#endif
 _start_skip_bss_init_array:
 	ldrh r2, =0x706             @ Disable + reset all counters. Cycle counter divider 1. IRQs disabled.
 	mcr p15, 0, r2, c15, c12, 0 @ Write Performance Monitor Control Register