diff --git a/include/arm9/hardware/crypto.h b/include/arm9/hardware/crypto.h
index 3c049c6..e8cae17 100644
--- a/include/arm9/hardware/crypto.h
+++ b/include/arm9/hardware/crypto.h
@@ -26,7 +26,7 @@
 //             AES              //
 //////////////////////////////////
 
-#define AES_MAX_BLOCKS        (0xFFFF)
+#define AES_MAX_BLOCKS        (0xFFFE) // Aligned for 32 bytes transfers
 
 #define AES_WRITE_FIFO_COUNT  (REG_AESCNT & 0x1F)
 #define AES_READ_FIFO_COUNT   (REG_AESCNT & 0x3E0)
diff --git a/source/arm9/hardware/crypto.c b/source/arm9/hardware/crypto.c
index 3696158..bf211cd 100644
--- a/source/arm9/hardware/crypto.c
+++ b/source/arm9/hardware/crypto.c
@@ -173,12 +173,12 @@
 
 	REG_NDMA0_DST_ADDR = REG_AESWRFIFO;
 	REG_NDMA0_INT_CNT = NDMA_INT_SYS_FREQ;
-	REG_NDMA0_CNT = NDMA_TOTAL_CNT_MODE | NDMA_STARTUP_AES_IN |
+	REG_NDMA0_CNT = NDMA_TOTAL_CNT_MODE | NDMA_STARTUP_AES_IN | NDMA_BURST_SIZE(4) |
 	                NDMA_SRC_UPDATE_INC | NDMA_DST_UPDATE_FIXED;
 
 	REG_NDMA1_SRC_ADDR = REG_AESRDFIFO;
 	REG_NDMA1_INT_CNT = NDMA_INT_SYS_FREQ;
-	REG_NDMA1_CNT = NDMA_TOTAL_CNT_MODE | NDMA_STARTUP_AES_OUT |
+	REG_NDMA1_CNT = NDMA_TOTAL_CNT_MODE | NDMA_STARTUP_AES_OUT | NDMA_BURST_SIZE(4) |
 	                NDMA_SRC_UPDATE_FIXED | NDMA_DST_UPDATE_INC;
 
 	IRQ_registerHandler(IRQ_AES, NULL);
@@ -338,17 +338,19 @@
 
 	for(u32 i = 0; i < blocks * 4; i += 4)
 	{
-		*((vu32*)REG_AESWRFIFO) = in[0 + i];
-		*((vu32*)REG_AESWRFIFO) = in[1 + i];
-		*((vu32*)REG_AESWRFIFO) = in[2 + i];
-		*((vu32*)REG_AESWRFIFO) = in[3 + i];
+		_u128 tmp = *((const _u128*)&in[i]);
+		*((vu32*)REG_AESWRFIFO) = tmp.block[0];
+		*((vu32*)REG_AESWRFIFO) = tmp.block[1];
+		*((vu32*)REG_AESWRFIFO) = tmp.block[2];
+		*((vu32*)REG_AESWRFIFO) = tmp.block[3];
 
 		while(AES_READ_FIFO_COUNT == 0);
 
-		out[0 + i] = *((vu32*)REG_AESRDFIFO);
-		out[1 + i] = *((vu32*)REG_AESRDFIFO);
-		out[2 + i] = *((vu32*)REG_AESRDFIFO);
-		out[3 + i] = *((vu32*)REG_AESRDFIFO);
+		tmp.block[0] = *((vu32*)REG_AESRDFIFO);
+		tmp.block[1] = *((vu32*)REG_AESRDFIFO);
+		tmp.block[2] = *((vu32*)REG_AESRDFIFO);
+		tmp.block[3] = *((vu32*)REG_AESRDFIFO);
+		*((_u128*)&out[i]) = tmp;
 	}
 }
 
@@ -361,32 +363,19 @@
 
 
 	// Check block alignment
-	u32 aesFifoSize, dmaBurstSize;
-	if(!(blocks & 3) || blocks == AES_MAX_BLOCKS)
-	{
-		aesFifoSize = 3;
-		dmaBurstSize = NDMA_BURST_SIZE(16);
-	}
-	else if(!(blocks & 1))
-	{
-		aesFifoSize = 1;
-		dmaBurstSize = NDMA_BURST_SIZE(8);
-	}
-	else
-	{
-		aesFifoSize = 0;
-		dmaBurstSize = NDMA_BURST_SIZE(4);
-	}
+	u32 aesFifoSize;
+	if(!(blocks & 1)) aesFifoSize = 1; // 32 bytes
+	else              aesFifoSize = 0; // 16 bytes
 
 	REG_NDMA0_SRC_ADDR = (u32)in;
 	REG_NDMA0_TOTAL_CNT = blocks<<2;
 	REG_NDMA0_LOG_BLK_CNT = aesFifoSize * 4 + 4;
-	REG_NDMA0_CNT = (REG_NDMA0_CNT & 0xFFF0FFFFu) | NDMA_ENABLE | dmaBurstSize;
+	REG_NDMA0_CNT |= NDMA_ENABLE;
 
 	REG_NDMA1_DST_ADDR = (u32)out;
 	REG_NDMA1_TOTAL_CNT = blocks<<2;
 	REG_NDMA1_LOG_BLK_CNT = aesFifoSize * 4 + 4;
-	REG_NDMA1_CNT = (REG_NDMA1_CNT & 0xFFF0FFFFu) | NDMA_ENABLE | dmaBurstSize;
+	REG_NDMA1_CNT |= NDMA_ENABLE;
 
 	REG_AES_BLKCNT_HIGH = blocks;
 	REG_AESCNT |= AES_ENABLE | AES_IRQ_ENABLE | aesFifoSize<<14 | (3 - aesFifoSize)<<12 |
@@ -418,10 +407,6 @@
 		if(dma) aesProcessBlocksDma(in, out, blockNum);
 		else aesProcessBlocksCpu(in, out, blockNum);
 
-		// AES will process 64 bytes for the last block of the
-		// block transfer even if only 48 are setup (0xFFFF vs. 0x10000 blocks).
-		if(dma && blockNum == AES_MAX_BLOCKS) blockNum++;
-
 		AES_addCounter(ctr, blockNum<<4);
 		in += blockNum<<2;
 		out += blockNum<<2;
@@ -516,10 +501,6 @@
 		if(dma) aesProcessBlocksDma(in, out, blockNum);
 		else aesProcessBlocksCpu(in, out, blockNum);
 
-		// AES will process 64 bytes for the last block of the
-		// block transfer even if only 48 are setup (0xFFFF vs. 0x10000 blocks).
-		if(dma && blockNum == AES_MAX_BLOCKS) blockNum++;
-
 		in += blockNum<<2;
 		out += blockNum<<2;
 		blocks -= blockNum;