diff --git a/include/arm11/debug.h b/include/arm11/debug.h
index 96ba5ee..f5c7f70 100644
--- a/include/arm11/debug.h
+++ b/include/arm11/debug.h
@@ -30,23 +30,23 @@
 // Exception tests
 /*static inline regTest(void)
 {
-	__asm__ __volatile__("mov r0, #1\n\tmov r1, #2\n\tmov r2, #3\n\tmov r3, #4\n\tmov r4, #5\n\t"
-	                     "mov r5, #6\n\tmov r6, #7\n\tmov r7, #8\n\tmov r8, #9\n\tmov r9, #10\n\t"
-	                     "mov r10, #11\n\tmov r11, #12\n\tmov r12, #13\n\tmov r13, #14\n\t"
-	                     "mov r14, #15\n\tmov r15, #16\n\t" : :);
+	__asm__ volatile("mov r0, #1\n\tmov r1, #2\n\tmov r2, #3\n\tmov r3, #4\n\tmov r4, #5\n\t"
+	                 "mov r5, #6\n\tmov r6, #7\n\tmov r7, #8\n\tmov r8, #9\n\tmov r9, #10\n\t"
+	                 "mov r10, #11\n\tmov r11, #12\n\tmov r12, #13\n\tmov r13, #14\n\t"
+	                 "mov r14, #15\n\tmov r15, #16\n\t" : :);
 }
 
 static inline breakpointTest(void)
 {
-	__asm__ __volatile__("bkpt #0xCAFE" : :);
+	__asm__ volatile("bkpt #0xCAFE" : :);
 }
 
 static inline dataAbortTest(void)
 {
-	__asm__ __volatile__("mov r0, #4\n\tmov r1, #0xEF\n\tstr r1, [r0]" : :);
+	__asm__ volatile("mov r0, #4\n\tmov r1, #0xEF\n\tstr r1, [r0]" : :);
 }
 
 static inline undefInstrTest(void)
 {
-	__asm__ __volatile__(".word 0xFFFFFFFF" : :);
+	__asm__ volatile(".word 0xFFFFFFFF" : :);
 }*/
diff --git a/include/arm11/event.h b/include/arm11/event.h
index 19b40f2..b4e337b 100644
--- a/include/arm11/event.h
+++ b/include/arm11/event.h
@@ -22,10 +22,10 @@
 
 static inline void __wfe(void)
 {
-	__asm__ __volatile__("wfe" : : : "memory");
+	__asm__ volatile("wfe" : : : "memory");
 }
 
 static inline void __sev(void)
 {
-	__asm__ __volatile__("sev" : : : "memory");
+	__asm__ volatile("sev" : : : "memory");
 }
\ No newline at end of file
diff --git a/include/arm11/hardware/interrupt.h b/include/arm11/hardware/interrupt.h
index 78dd961..9264fba 100644
--- a/include/arm11/hardware/interrupt.h
+++ b/include/arm11/hardware/interrupt.h
@@ -127,20 +127,20 @@
 
 static inline void __wfi(void)
 {
-	__asm__ __volatile__("wfi" : : : "memory");
+	__asm__ volatile("wfi" : : : "memory");
 }
 
 static inline u32 enterCriticalSection(void)
 {
 	u32 tmp;
 	__asm__("mrs %0, cpsr" : "=r" (tmp) : );
-	__asm__ __volatile__("cpsid i" : : : "memory");
+	__asm__ volatile("cpsid i" : : : "memory");
 	return tmp & 0x80;
 }
 
 static inline void leaveCriticalSection(u32 oldState)
 {
 	u32 tmp;
-	__asm__ __volatile__("mrs %0, cpsr" : "=r" (tmp) : );
-	__asm__ __volatile__("msr cpsr_c, %0" : : "r" ((tmp & ~0x80u) | oldState) : "memory");
+	__asm__ volatile("mrs %0, cpsr" : "=r" (tmp) : );
+	__asm__ volatile("msr cpsr_c, %0" : : "r" ((tmp & ~0x80u) | oldState) : "memory");
 }
diff --git a/include/arm11/spinlock.h b/include/arm11/spinlock.h
index 3c52109..e430a27 100644
--- a/include/arm11/spinlock.h
+++ b/include/arm11/spinlock.h
@@ -25,21 +25,21 @@
 static inline void spinlockLock(u32 *lock)
 {
 	u32 tmp;
-	__asm__ __volatile__("1: ldrex %0, [%1]\n"
-	                     "   teq %0, #0\n"
-	                     "   wfene\n"
-	                     "   strexeq %0, %2, [%1]\n"
-	                     "   teqeq %0, #0\n"
-	                     "   bne 1b\n"
-	                     "   mcr p15, 0, %0, c7, c10, 5" // DMB
-	                     : "=&r" (tmp) : "r" (lock), "r" (1) : "cc", "memory");
+	__asm__ volatile("1: ldrex %0, [%1]\n"
+	                 "   teq %0, #0\n"
+	                 "   wfene\n"
+	                 "   strexeq %0, %2, [%1]\n"
+	                 "   teqeq %0, #0\n"
+	                 "   bne 1b\n"
+	                 "   mcr p15, 0, %0, c7, c10, 5" // DMB
+	                 : "=&r" (tmp) : "r" (lock), "r" (1) : "cc", "memory");
 }
 
 static inline void spinlockUnlock(u32 *lock)
 {
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5\n" // DMB
-	                     "str %0, [%1]\n"
-	                     "mcr p15, 0, %0, c7, c10, 4\n" // DSB
-	                     "sev"
-	                     : : "r" (0), "r" (lock) : "memory");
+	__asm__ volatile("mcr p15, 0, %0, c7, c10, 5\n" // DMB
+	                 "str %0, [%1]\n"
+	                 "mcr p15, 0, %0, c7, c10, 4\n" // DSB
+	                 "sev"
+	                 : : "r" (0), "r" (lock) : "memory");
 }
diff --git a/include/arm11/start.h b/include/arm11/start.h
index 064228b..4cb59b0 100644
--- a/include/arm11/start.h
+++ b/include/arm11/start.h
@@ -28,6 +28,6 @@
 static inline u32 getCpuId(void)
 {
 	u32 cpuId;
-	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 5" : "=r" (cpuId) : );
+	__asm__("mrc p15, 0, %0, c0, c0, 5" : "=r" (cpuId) : );
 	return cpuId & 3;
 }
diff --git a/include/arm9/hardware/interrupt.h b/include/arm9/hardware/interrupt.h
index e0770e1..99e438a 100644
--- a/include/arm9/hardware/interrupt.h
+++ b/include/arm9/hardware/interrupt.h
@@ -85,20 +85,20 @@
 
 static inline void __wfi(void)
 {
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c0, 4" : : "r" (0) : "memory");
+	__asm__ volatile("mcr p15, 0, %0, c7, c0, 4" : : "r" (0) : "memory");
 }
 
 static inline u32 enterCriticalSection(void)
 {
 	u32 tmp;
-	__asm__ __volatile__("mrs %0, cpsr" : "=r" (tmp) : );
-	__asm__ __volatile__("msr cpsr_c, %0" : : "r" (tmp | 0x80) : "memory");
+	__asm__ volatile("mrs %0, cpsr" : "=r" (tmp) : );
+	__asm__ volatile("msr cpsr_c, %0" : : "r" (tmp | 0x80) : "memory");
 	return tmp & 0x80;
 }
 
 static inline void leaveCriticalSection(u32 oldState)
 {
 	u32 tmp;
-	__asm__ __volatile__("mrs %0, cpsr" : "=r" (tmp) : );
-	__asm__ __volatile__("msr cpsr_c, %0" : : "r" ((tmp & ~0x80u) | oldState) : "memory");
+	__asm__ volatile("mrs %0, cpsr" : "=r" (tmp) : );
+	__asm__ volatile("msr cpsr_c, %0" : : "r" ((tmp & ~0x80u) | oldState) : "memory");
 }
diff --git a/source/arm11/firm.c b/source/arm11/firm.c
index a04a939..19f8f96 100644
--- a/source/arm11/firm.c
+++ b/source/arm11/firm.c
@@ -70,7 +70,7 @@
 	deinitCpu();
 
 	// Change sp to a safe location
-	__asm__ __volatile__("mov sp, %0" : : "r" (A11_STUB_ENTRY) : "sp");
+	__asm__ volatile("mov sp, %0" : : "r" (A11_STUB_ENTRY) : "sp");
 	((void (*)(void))A11_STUB_ENTRY)();
 	while(1);
 }
diff --git a/source/arm11/hardware/mmu.c b/source/arm11/hardware/mmu.c
index 45210c4..9f08217 100644
--- a/source/arm11/hardware/mmu.c
+++ b/source/arm11/hardware/mmu.c
@@ -108,13 +108,13 @@
 void setupMmu(void)
 {
 	// TTBR0 address shared page table walk and outer cachable write-through, no allocate on write
-	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 0" : : "r" (A11_MMU_TABLES_BASE | 0x12u));
+	__asm__ volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (A11_MMU_TABLES_BASE | 0x12u));
 	// Use the 16 KB L1 table only
-	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 2" : : "r" (0u));
+	__asm__ volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (0u));
 	// Domain 1 = client, remaining domains all = no access
-	__asm__ __volatile__("mcr p15, 0, %0, c3, c0, 0" : : "r" (4u));
+	__asm__ volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (4u));
 	// Context ID Register (ASID = 0, PROCID = 0)
-	__asm__ __volatile__("mcr p15, 0, %0, c13, c0, 1" : : "r" (0u));
+	__asm__ volatile("mcr p15, 0, %0, c13, c0, 1" : : "r" (0u));
 
 
 	static volatile bool syncFlag = false;
@@ -175,27 +175,27 @@
 
 
 	// Invalidate TLB (Unified TLB operation) + Data Synchronization Barrier
-	__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0\n"
-	                     "mcr p15, 0, %0, c7, c10, 4" : : "r" (0u));
+	__asm__ volatile("mcr p15, 0, %0, c8, c7, 0\n"
+	                 "mcr p15, 0, %0, c7, c10, 4" : : "r" (0u));
 
 
 	u32 tmp;
 	// Modify Auxiliary Control Register
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r" (tmp) : );
+	__asm__ volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (tmp) : );
 	tmp |= 0x6Fu;     // Enable Return stack, Dynamic branch prediction, Static branch prediction,
 	                  // Instruction folding, SMP mode: the CPU is taking part in coherency
 	                  // and L1 parity checking
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r" (tmp));
+	__asm__ volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (tmp));
 
 	// Modify Control Register
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0" : "=r" (tmp) : );
+	__asm__ volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (tmp) : );
 	tmp |= 0xC03805u; // Enable MMU, D-Cache, Program flow prediction,
 	                  // I-Cache, high exception vectors, Unaligned data access,
 	                  // subpage AP bits disabled
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0" : : "r" (tmp));
+	__asm__ volatile("mcr p15, 0, %0, c1, c0, 0" : : "r" (tmp));
 
 	// Invalidate all caches + Data Synchronization Barrier
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0\n"
-	                     "mcr p15, 0, %0, c7, c10, 4\n" // DSB
-	                     "mcr p15, 0, %0, c7, c5, 4" : : "r" (0u));
+	__asm__ volatile("mcr p15, 0, %0, c7, c7, 0\n"
+	                 "mcr p15, 0, %0, c7, c10, 4\n" // DSB
+	                 "mcr p15, 0, %0, c7, c5, 4" : : "r" (0u));
 }
diff --git a/source/arm11/power.c b/source/arm11/power.c
index 6e58242..d616d55 100644
--- a/source/arm11/power.c
+++ b/source/arm11/power.c
@@ -37,7 +37,7 @@
 	TIMER_sleepMs(400);
 
 	flushDCache();
-	__asm__ __volatile__("cpsid aif" : : : "memory");
+	__asm__ volatile("cpsid aif" : : : "memory");
 }
 
 noreturn void power_off(void)
diff --git a/source/arm11/system.c b/source/arm11/system.c
index 32f45cc..b4206b2 100644
--- a/source/arm11/system.c
+++ b/source/arm11/system.c
@@ -52,5 +52,5 @@
 		((void (*)(void))0x0001004C)();
 	}
 
-	__asm__ __volatile__("cpsie i" : : : "memory"); // Enables interrupts
+	__asm__ volatile("cpsie i" : : : "memory"); // Enables interrupts
 }