diff --git a/Makefile b/Makefile
index e57f682..b924a20 100644
--- a/Makefile
+++ b/Makefile
@@ -12,4 +12,4 @@
 code11.bin:
 	make -f Makefile.arm11
 firm.bin:
-	$(DEVKITARM)/bin/firm_builder firm.bin 0x08000040 0x1FF85000 0x08000040 0 code9.bin 0x1FF85000 1 code11.bin
+	$(DEVKITARM)/bin/firm_builder firm.bin 0x08000040 0x1FF85040 0x08000040 0 code9.bin 0x1FF85000 1 code11.bin
diff --git a/source/arm11/cpu.s b/source/arm11/cpu.s
index 7b1e1b7..d776c4a 100644
--- a/source/arm11/cpu.s
+++ b/source/arm11/cpu.s
@@ -8,7 +8,7 @@
 .global deinitCpu
 
 .type initCpu STT_FUNC
-.type setupExceptionVectors STT_FUNC
+.type stubExceptionVectors STT_FUNC
 .type setupVfp STT_FUNC
 .type deinitCpu STT_FUNC
 
@@ -49,37 +49,25 @@
 
 	ldr sp, =A11_STACK_END
 
-	bl setupExceptionVectors    @ Setup the vectors in AXIWRAM bootrom vectors jump to
-	bl setupVfp
+	bl stubExceptionVectors     @ Stub the vectors in AXIWRAM bootrom vectors jump to
 	blx setupMmu
+	bl setupVfp
+	cpsie a
 	bx r10
 .pool
 
 
 #define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF))
 
-setupExceptionVectors:
-	adr r0, __vectorStubs
-	ldr r1, =A11_VECTORS_START
-	ldmia r0!, {r2-r9}
-	stmia r1!, {r2-r9}
-	ldmia r0, {r2-r5}
-	stmia r1, {r2-r5}
+stubExceptionVectors:
+	ldr r0, =A11_VECTORS_START
+	mov r1, #6
+	ldr r2, =MAKE_BRANCH(0, 0)  @ Endless loop
+	stubExceptionVectors_lp:
+		str r2, [r0], #8
+		subs r1, r1, #1
+		bne stubExceptionVectors_lp
 	bx lr
-.pool
-__vectorStubs:
-	.word MAKE_BRANCH(A11_VECTORS_START + 0x00, A11_VECTORS_START + 0x00) // IRQ
-	.word 0
-	.word MAKE_BRANCH(A11_VECTORS_START + 0x08, A11_VECTORS_START + 0x08) // FIQ
-	.word 0
-	.word MAKE_BRANCH(A11_VECTORS_START + 0x10, A11_VECTORS_START + 0x10) // SVC
-	.word 0
-	.word MAKE_BRANCH(A11_VECTORS_START + 0x18, A11_VECTORS_START + 0x18) // Undefined instruction
-	.word 0
-	.word MAKE_BRANCH(A11_VECTORS_START + 0x20, A11_VECTORS_START + 0x20) // Prefetch abort
-	.word 0
-	.word MAKE_BRANCH(A11_VECTORS_START + 0x28, A11_VECTORS_START + 0x28) // Data abort
-	.word 0
 
 
 setupVfp:
@@ -96,17 +84,10 @@
 
 
 deinitCpu:
-	mov r4, lr
+	cpsid aif, #0x1F
+	mov r3, lr
 
-	@ Stub vectors to endless loops
-	ldr r0, =A11_VECTORS_START
-	mov r1, #6
-	ldr r2, =MAKE_BRANCH(0, 0)  @ Endless loop
-	deinitCpu_vector_lp:
-		str r2, [r0], #8
-		subs r1, r1, #1
-		bne deinitCpu_vector_lp
-
+	bl stubExceptionVectors
 	bl flushDCache
 	mov r2, #0
 	mrc p15, 0, r0, c1, c0, 0   @ Read control register
@@ -125,8 +106,9 @@
 	mcr p15, 0, r2, c7, c7, 0   @ Invalidate Both Caches. Also flushes the branch target cache
 	mcr p15, 0, r2, c7, c10, 4  @ Data Synchronization Barrier
 	clrex
+
 	@ Disable VFP11
 	fmxr fpscr, r2              @ Write Floating-Point Status and Control Register
 	fmxr fpexc, r2              @ Write Floating-point exception register
-	bx r4
+	bx r3
 .pool
diff --git a/source/arm11/mmu.c b/source/arm11/mmu.c
index 5baac7f..85fb60f 100644
--- a/source/arm11/mmu.c
+++ b/source/arm11/mmu.c
@@ -59,6 +59,7 @@
 
 /**
  * @brief      Maps up to 128 4 KB pages of memory.
+ * @brief      The mapped range must not cross the next section.
  *
  * @param[in]  va       The virtual address base. Must be aligned to 4 KB.
  * @param[in]  pa       The physical address base. Must be aligned to 4 KB.
@@ -118,8 +119,8 @@
 				(u32*)(A11_MMU_TABLES_BASE + 0x4400u), true, PERM_PRIV_RW_USR_NO_ACC, 1, false,
 				L1_TO_L2(MAKE_CUSTOM_NORM_ATTR(POLICY_WRITE_BACK_ALLOC_BUFFERED, POLICY_WRITE_BACK_ALLOC_BUFFERED)));
 
-	// boot11 mirror mapping (exception vectors)
-	mmuMapPages(BOOT11_MIRROR2, BOOT11_MIRROR2, 8, (u32*)(A11_MMU_TABLES_BASE + 0x4800u), true,
+	// Map boot11 mirror to loader executable start (exception vectors)
+	mmuMapPages(BOOT11_MIRROR2, AXIWRAM_BASE + 0x5000u, 1, (u32*)(A11_MMU_TABLES_BASE + 0x4800u), true,
 				PERM_PRIV_RO_USR_NO_ACC, 1, false,
 				L1_TO_L2(MAKE_CUSTOM_NORM_ATTR(POLICY_WRITE_BACK_ALLOC_BUFFERED, POLICY_WRITE_BACK_ALLOC_BUFFERED)));
 
@@ -150,7 +151,4 @@
 	                  // Program flow prediction, I-Cache, high exception vectors,
 	                  // subpage AP bits disabled
 	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r" (tmp));
-
-	// Flush Prefetch Buffer
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4\n\t" : : "r" (0u));
 }
diff --git a/source/arm11/start.s b/source/arm11/start.s
index 0231846..be43740 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -6,6 +6,7 @@
 .global clearMem
 .global _init
 
+.type vectors STT_FUNC
 .type _start STT_FUNC
 .type clearMem STT_FUNC
 .type _init STT_FUNC
@@ -22,6 +23,18 @@
 
 
 
+_vectors:
+	ldr pc, =_start            @ Reset vector
+	ldr pc, =(_vectors + 0x04) @ Undefined instruction vector
+	ldr pc, =(_vectors + 0x08) @ Software interrupt (SVC) vector
+	ldr pc, =(_vectors + 0x0C) @ Prefetch abort vector
+	ldr pc, =(_vectors + 0x10) @ Data abort vector
+	ldr pc, =(_vectors + 0x14) @ Reserved (unused) vector
+	ldr pc, =(_vectors + 0x18) @ Interrupt (IRQ) vector
+	ldr pc, =(_vectors + 0x1C) @ Fast interrupt (FIQ) vector
+.pool
+
+
 _start:
 	cpsid aif, #0x1F           @ Disable all interrupts, system mode
 
diff --git a/source/arm9/cpu.s b/source/arm9/cpu.s
index 93925a4..4a4e2a2 100644
--- a/source/arm9/cpu.s
+++ b/source/arm9/cpu.s
@@ -46,9 +46,9 @@
 	mcr p15, 0, r0, c7, c10, 4  @ Drain write buffer
 
 	bl setupExceptionVectors    @ Setup the vectors in ARM9 mem bootrom vectors jump to
+	bl setupMpu
 	bl setupTcms                @ Setup and enable DTCM and ITCM
 	ldr sp, =A9_STACK_END
-	bl setupMpu
 	bx r10
 .pool
 
@@ -225,6 +225,7 @@
 
 
 deinitCpu:
+	msr cpsr_cxsf, #0xDF
 	mov r4, lr
 
 	@ Stub vectors to endless loops