diff --git a/include/arm11/hardware/interrupt.h b/include/arm11/hardware/interrupt.h
index 594771e..a30b15a 100644
--- a/include/arm11/hardware/interrupt.h
+++ b/include/arm11/hardware/interrupt.h
@@ -87,6 +87,8 @@
IRQ_PXI_NOT_EMPTY = 83,
IRQ_I2C1 = 84,
IRQ_I2C2 = 85,
+ IRQ_SPI3 = 86, // SPI bus 3 interrupt status update
+ IRQ_SPI1 = 87, // SPI bus 1 interrupt status update
IRQ_PDN = 88,
IRQ_I2C3 = 92,
IRQ_SHELL_OPENED = 96,
diff --git a/include/arm11/hardware/spi.h b/include/arm11/hardware/spi.h
index b227de3..aa3306a 100644
--- a/include/arm11/hardware/spi.h
+++ b/include/arm11/hardware/spi.h
@@ -21,14 +21,39 @@
#include "types.h"
-// SPI_NEW_CNT
-#define SPI_CNT_DIRE_READ (0u)
-#define SPI_CNT_DIRE_WRITE (1u<<13)
-#define SPI_CNT_ENABLE (1u<<15)
+// REG_NSPI_CNT
+#define NSPI_CNT_BUS_1BIT (0u)
+#define NSPI_CNT_BUS_4BIT (1u<<12)
+#define NSPI_CNT_DIRE_READ (0u)
+#define NSPI_CNT_DIRE_WRITE (1u<<13)
+#define NSPI_CNT_ENABLE (1u<<15)
-// SPI_NEW_STATUS
-#define SPI_STATUS_BUSY (1u)
+// REG_NSPI_DONE
+#define NSPI_DONE_DONE (0u)
+// REG_NSPI_STATUS
+#define NSPI_STATUS_BUSY (1u)
+
+// REG_NSPI_AUTOPOLL
+#define NSPI_AUTOPOLL_START (1u<<31)
+
+// REG_NSPI_INT_MASK Bit set = disabled.
+// REG_NSPI_INT_STAT Status and aknowledge.
+#define NSPI_INT_UNK (1u) // Fires on auto poll success aswell. Transfer finished?
+#define NSPI_INT_AP_SUCCESS (1u<<1) // Auto poll
+#define NSPI_INT_AP_TIMEOUT (1u<<2) // Auto poll
+
+
+// TODO: Confirm these clocks
+enum
+{
+ NSPI_CLK_128KHz = 0,
+ NSPI_CLK_256KHz = 1,
+ NSPI_CLK_512KHz = 2,
+ NSPI_CLK_1MHz = 3,
+ NSPI_CLK_2MHz = 4,
+ NSPI_CLK_4MHz = 5,
+};
// TODO: Proper device table
typedef enum
@@ -39,7 +64,7 @@
SPI_DEV_CODEC = 3,
SPI_DEV_UNK5 = 4,
SPI_DEV_UNK6 = 5,
- SPI_DEV_UNK7 = 6,
+ SPI_DEV_UNK7 = 6 // Don't use autopoll on this.
} SpiDevice;
@@ -47,7 +72,20 @@
/**
* @brief Initializes the SPI buses. Call this only once.
*/
-void SPI_init(void);
+void NSPI_init(void);
+
+/**
+ * @brief Automatically polls a bit of the command response.
+ *
+ * @param[in] dev The device ID. See table above.
+ * @param[in] cmd The command.
+ * @param[in] timeout The timeout. Must be 0-15. Tries = 31<.
+ */
+
+#include "types.h"
+
+
+// REG_NSPI_CNT
+#define NSPI_CNT_BUS_1BIT (0u)
+#define NSPI_CNT_BUS_4BIT (1u<<12)
+#define NSPI_CNT_DIRE_READ (0u)
+#define NSPI_CNT_DIRE_WRITE (1u<<13)
+#define NSPI_CNT_ENABLE (1u<<15)
+
+// REG_NSPI_DONE
+#define NSPI_DONE (0u)
+
+// REG_NSPI_STATUS
+#define NSPI_STATUS_BUSY (1u)
+
+// REG_NSPI_AUTOPOLL
+#define NSPI_AUTOPOLL_START (1u<<31)
+
+// REG_NSPI_INT_MASK Bit set = disabled.
+// REG_NSPI_INT_STAT Status and aknowledge.
+#define NSPI_INT_UNK (1u) // Fires on auto poll success aswell. Transfer finished?
+#define NSPI_INT_AP_SUCCESS (1u<<1) // Auto poll
+#define NSPI_INT_AP_TIMEOUT (1u<<2) // Auto poll
+
+
+typedef enum
+{
+ NSPI_CLK_512KHz = 0,
+ NSPI_CLK_1MHz = 1,
+ NSPI_CLK_2MHz = 2,
+ NSPI_CLK_4MHz = 3,
+ NSPI_CLK_8MHz = 4,
+ NSPI_CLK_16MHz = 5
+} NspiClk;
+
+
+
+/**
+ * @brief Initializes the SPI buses. Call this only once.
+ */
+void SPICARD_init(void);
+
+/**
+ * @brief Automatically polls a bit of the command response.
+ *
+ * @param[in] cmd The command.
+ * @param[in] timeout The timeout. Must be 0-15. Tries = 31<SPI_NEW_CNT & SPI_CNT_ENABLE);
+ while(regs->NSPI_CNT & NSPI_CNT_ENABLE);
}
-static void spiWaitFifoBusy(const SpiRegs *const regs)
+static void nspiWaitFifoBusy(const SpiRegs *const regs)
{
- while(regs->SPI_NEW_STATUS & SPI_STATUS_BUSY);
+ while(regs->NSPI_STATUS & NSPI_STATUS_BUSY);
}
-void SPI_init(void)
+void NSPI_init(void)
{
static bool inited = false;
if(inited) return;
@@ -111,43 +103,76 @@
// Switch all 3 buses to the new interface
REG_CFG11_SPI_CNT = 1u<<2 | 1u<<1 | 1u;
+
+ IRQ_registerHandler(IRQ_SPI3, 14, 0, true, NULL);
+ IRQ_registerHandler(IRQ_SPI1, 14, 0, true, NULL);
+
+ SpiRegs *regs = nspiGetBusRegsBase(SPI_BUS1);
+ regs->NSPI_INT_MASK = NSPI_INT_UNK; // Disable interrupt 1
+ regs->NSPI_INT_STAT = NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS | NSPI_INT_UNK; // Aknowledge
+
+ regs = nspiGetBusRegsBase(SPI_BUS2);
+ // Disable all since there is no interrupt for this bus.
+ regs->NSPI_INT_MASK = NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS | NSPI_INT_UNK;
+ regs->NSPI_INT_STAT = NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS | NSPI_INT_UNK;
+
+ regs = nspiGetBusRegsBase(SPI_BUS3);
+ regs->NSPI_INT_MASK = NSPI_INT_UNK;
+ regs->NSPI_INT_STAT = NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS | NSPI_INT_UNK;
}
-void SPI_writeRead(SpiDevice dev, const u32 *in, u32 *out, u32 inSize, u32 outSize, bool done)
+bool NSPI_autoPollBit(SpiDevice dev, u8 cmd, u8 timeout, u8 off, bool bitSet)
{
- SpiRegs *const regs = spiGetBusRegsBase(spiDevTable[dev].busId);
- const u32 cntParams = SPI_CNT_ENABLE | spiDevTable[dev].csBaud;
+ SpiRegs *const regs = nspiGetBusRegsBase(spiDevTable[dev].busId);
+
+ regs->NSPI_AUTOPOLL = NSPI_AUTOPOLL_START | bitSet<<30 | off<<24 | timeout<<16 | cmd;
+
+ u32 res;
+ do
+ {
+ __wfi();
+ res = regs->NSPI_INT_STAT;
+ } while(!(res & (NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS)));
+ regs->NSPI_INT_STAT = res; // Aknowledge
+
+ return (res & NSPI_INT_AP_TIMEOUT) == 0; // Timeout error
+}
+
+void NSPI_writeRead(SpiDevice dev, const u32 *in, u32 *out, u32 inSize, u32 outSize, bool done)
+{
+ SpiRegs *const regs = nspiGetBusRegsBase(spiDevTable[dev].busId);
+ const u32 cntParams = NSPI_CNT_ENABLE | spiDevTable[dev].csClk;
if(in)
{
- regs->SPI_NEW_BLKLEN = inSize;
- regs->SPI_NEW_CNT = cntParams | SPI_CNT_DIRE_WRITE;
+ regs->NSPI_BLKLEN = inSize;
+ regs->NSPI_CNT = cntParams | NSPI_CNT_DIRE_WRITE;
u32 counter = 0;
do
{
- if((counter & 31) == 0) spiWaitFifoBusy(regs);
- regs->SPI_NEW_FIFO = *in++;
+ if((counter & 31) == 0) nspiWaitFifoBusy(regs);
+ regs->NSPI_FIFO = *in++;
counter += 4;
} while(counter < inSize);
- spiWaitBusy(regs);
+ nspiWaitBusy(regs);
}
if(out)
{
- regs->SPI_NEW_BLKLEN = outSize;
- regs->SPI_NEW_CNT = cntParams | SPI_CNT_DIRE_READ;
+ regs->NSPI_BLKLEN = outSize;
+ regs->NSPI_CNT = cntParams | NSPI_CNT_DIRE_READ;
u32 counter = 0;
do
{
- if((counter & 31) == 0) spiWaitFifoBusy(regs);
- *out++ = regs->SPI_NEW_FIFO;
+ if((counter & 31) == 0) nspiWaitFifoBusy(regs);
+ *out++ = regs->NSPI_FIFO;
counter += 4;
} while(counter < outSize);
- spiWaitBusy(regs);
+ nspiWaitBusy(regs);
}
- if(done) regs->SPI_NEW_DONE = 0;
+ if(done) regs->NSPI_DONE = NSPI_DONE_DONE;
}
diff --git a/source/arm11/hardware/spiflash.c b/source/arm11/hardware/spiflash.c
index 5dd3978..2f30348 100644
--- a/source/arm11/hardware/spiflash.c
+++ b/source/arm11/hardware/spiflash.c
@@ -27,7 +27,7 @@
alignas(4) u8 cmd[4];
cmd[0] = SPIFLASH_CMD_RDSR;
- SPI_writeRead(SPI_DEV_NVRAM, (u32*)cmd, (u32*)cmd, 1, 1, true);
+ NSPI_writeRead(SPI_DEV_NVRAM, (u32*)cmd, (u32*)cmd, 1, 1, true);
if(cmd[0] & 1) return false;
return true;
@@ -37,5 +37,5 @@
{
offset = __builtin_bswap32(offset & 0x00FFFFFFu) | SPIFLASH_CMD_READ;
- SPI_writeRead(SPI_DEV_NVRAM, &offset, buf, 4, size, true);
+ NSPI_writeRead(SPI_DEV_NVRAM, &offset, buf, 4, size, true);
}
diff --git a/source/arm9/hardware/spicard.c b/source/arm9/hardware/spicard.c
new file mode 100644
index 0000000..0e0fc01
--- /dev/null
+++ b/source/arm9/hardware/spicard.c
@@ -0,0 +1,143 @@
+/*
+ * This file is part of fastboot 3DS
+ * Copyright (C) 2019 derrek, profi200
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include "types.h"
+#include "mem_map.h"
+#include "arm9/hardware/spicard.h"
+#include "arm9/hardware/cfg9.h"
+#include "arm9/hardware/interrupt.h"
+#include "arm9/hardware/timer.h"
+#include "arm9/hardware/ndma.h"
+
+
+#define SPICARD_REGS_BASE (IO_MEM_ARM9_ONLY + 0xD800)
+#define REG_NSPI_CNT *((vu32*)(SPICARD_REGS_BASE + 0x00))
+#define REG_NSPI_DONE *((vu32*)(SPICARD_REGS_BASE + 0x04))
+#define REG_NSPI_BLKLEN *((vu32*)(SPICARD_REGS_BASE + 0x08))
+#define REG_NSPI_FIFO *((vu32*)(SPICARD_REGS_BASE + 0x0C))
+#define REG_NSPI_STATUS *((vu32*)(SPICARD_REGS_BASE + 0x10))
+#define REG_NSPI_AUTOPOLL *((vu32*)(SPICARD_REGS_BASE + 0x14))
+#define REG_NSPI_INT_MASK *((vu32*)(SPICARD_REGS_BASE + 0x18))
+#define REG_NSPI_INT_STAT *((vu32*)(SPICARD_REGS_BASE + 0x1C))
+
+
+
+static void nspiWaitBusy(void)
+{
+ while(REG_NSPI_CNT & NSPI_CNT_ENABLE);
+}
+
+static void nspiWaitFifoBusy(void)
+{
+ while(REG_NSPI_STATUS & NSPI_STATUS_BUSY);
+}
+
+void SPICARD_init(void)
+{
+ static bool inited = false;
+ if(inited) return;
+ inited = true;
+
+ // TODO
+#define REG_CFG9_CARDCTL *((vu16*)0x1000000C)
+#define REG_CFG9_CARDSTATUS *((vu8* )0x10000010)
+#define REG_CFG9_CARDCYCLES0 *((vu16*)0x10000012)
+#define REG_CFG9_CARDCYCLES1 *((vu16*)0x10000014)
+
+#define REG_NTRCARDMCNT *((vu16*)0x10164000)
+#define REG_NTRCARDROMCNT *((vu32*)0x10164004)
+
+ REG_CFG9_CARDCYCLES0 = 0x1988;
+ REG_CFG9_CARDCYCLES1 = 0x264C;
+ // boot9 waits here. Unnecessary?
+
+ REG_CFG9_CARDSTATUS = 3u<<2; // Request power off
+ while(REG_CFG9_CARDSTATUS != 0); // Aotomatically changes to 0 (off)
+ TIMER_sleep(1);
+
+ REG_CFG9_CARDSTATUS = 1u<<2; // Prepare power on
+ TIMER_sleep(10);
+
+ REG_CFG9_CARDSTATUS = 2u<<2; // Power on
+ TIMER_sleep(27);
+
+ // Switch to NTRCARD controller.
+ REG_CFG9_CARDCTL = 0;
+ REG_NTRCARDMCNT = 0xC000u;
+ REG_NTRCARDROMCNT = 0x20000000;
+ TIMER_sleep(120);
+
+ REG_CFG9_CARDCTL |= 1u<<8;
+
+ IRQ_registerHandler(IRQ_CTR_CARD_1, NULL);
+ REG_NSPI_INT_MASK = NSPI_INT_UNK; // Disable interrupt 1
+ REG_NSPI_INT_STAT = NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS | NSPI_INT_UNK; // Aknowledge
+}
+
+bool SPICARD_autoPollBit(u8 cmd, u8 timeout, u8 off, bool bitSet)
+{
+ REG_NSPI_AUTOPOLL = NSPI_AUTOPOLL_START | bitSet<<30 | off<<24 | timeout<<16 | cmd;
+
+ u32 res;
+ do
+ {
+ __wfi();
+ res = REG_NSPI_INT_STAT;
+ } while(!(res & (NSPI_INT_AP_TIMEOUT | NSPI_INT_AP_SUCCESS)));
+ REG_NSPI_INT_STAT = res; // Aknowledge
+
+ return (res & NSPI_INT_AP_TIMEOUT) == 0; // Timeout error
+}
+
+void SPICARD_writeRead(NspiClk clk, const u32 *in, u32 *out, u32 inSize, u32 outSize, bool done)
+{
+ const u32 cntParams = NSPI_CNT_ENABLE | NSPI_CNT_BUS_1BIT | clk;
+
+ if(in)
+ {
+ REG_NSPI_BLKLEN = inSize;
+ REG_NSPI_CNT = cntParams | NSPI_CNT_DIRE_WRITE;
+
+ u32 counter = 0;
+ do
+ {
+ if((counter & 31) == 0) nspiWaitFifoBusy();
+ REG_NSPI_FIFO = *in++;
+ counter += 4;
+ } while(counter < inSize);
+
+ nspiWaitBusy();
+ }
+ if(out)
+ {
+ REG_NSPI_BLKLEN = outSize;
+ REG_NSPI_CNT = cntParams | NSPI_CNT_DIRE_READ;
+
+ u32 counter = 0;
+ do
+ {
+ if((counter & 31) == 0) nspiWaitFifoBusy();
+ *out++ = REG_NSPI_FIFO;
+ counter += 4;
+ } while(counter < outSize);
+
+ nspiWaitBusy();
+ }
+
+ if(done) REG_NSPI_DONE = NSPI_DONE;
+}