diff --git a/include/mem_map.h b/include/mem_map.h
index 9676335..53dd405 100644
--- a/include/mem_map.h
+++ b/include/mem_map.h
@@ -25,7 +25,7 @@
 #define ITCM_BASE            (0x00000000)
 #define ITCM_KERNEL_MIRROR   (0x01FF8000)
 #define ITCM_BOOT9_MIRROR    (0x07FF8000)
-#define ITCM_SIZE            (0x00008000) // 32 KB
+#define ITCM_SIZE            (0x00008000) // 32 KiB
 #endif
 
 
@@ -33,7 +33,7 @@
 /* ARM11 bootrom */
 #define BOOT11_BASE          (0x00000000)
 #define BOOT11_MIRROR1       (0x00010000)
-#define BOOT11_SIZE          (0x00010000) // 64 KB
+#define BOOT11_SIZE          (0x00010000) // 64 KiB
 #endif
 
 
@@ -41,8 +41,8 @@
 /* ARM9 RAM */
 #define A9_RAM_BASE          (0x08000000)
 #define A9_RAM_N3DS_EXT_BASE (A9_RAM_BASE + 0x100000)
-#define A9_RAM_SIZE          (0x00100000) // 1 MB
-#define A9_RAM_N3DS_EXT_SIZE (0x00080000) // 512 KB
+#define A9_RAM_SIZE          (0x00100000) // 1 MiB
+#define A9_RAM_N3DS_EXT_SIZE (0x00080000) // 512 KiB
 #endif
 
 
@@ -56,12 +56,12 @@
 #ifdef ARM11
 /* ARM11 MPCore private region */
 #define MPCORE_PRIV_REG_BASE (0x17E00000)
-#define MPCORE_PRIV_REG_SIZE (0x00002000) // 8 KB
+#define MPCORE_PRIV_REG_SIZE (0x00002000) // 8 KiB
 
 
 /* L2C-310 Level 2 Cache Controller */
 #define L2_CACHE_CONTR_BASE  (0x17E10000)
-#define L2_CACHE_CONTR_SIZE  (0x00001000) // 4 KB
+#define L2_CACHE_CONTR_SIZE  (0x00001000) // 4 KiB
 #endif
 
 
@@ -74,35 +74,35 @@
 
 /* DSP mem */
 #define DSP_MEM_BASE         (0x1FF00000)
-#define DSP_MEM_SIZE         (0x00080000) // 512 KB
+#define DSP_MEM_SIZE         (0x00080000) // 512 KiB
 
 
 /* AXIWRAM */
 #define AXIWRAM_BASE         (0x1FF80000)
-#define AXIWRAM_SIZE         (0x00080000) // 512 KB
+#define AXIWRAM_SIZE         (0x00080000) // 512 KiB
 
 
 /* FCRAM */
 #define FCRAM_BASE           (0x20000000)
 #define FCRAM_N3DS_EXT_BASE  (FCRAM_BASE + 0x8000000)
-#define FCRAM_SIZE           (0x08000000) // 128 MB
+#define FCRAM_SIZE           (0x08000000) // 128 MiB
 #define FCRAM_N3DS_EXT_SIZE  (FCRAM_SIZE)
 
 
+#ifdef ARM9
 /* OTP */
 #define OTP_BASE         	 (0x10012000)
-#define OTP_SIZE         	 (0x00000100) // 256 byte
+#define OTP_SIZE         	 (0x00000100) // 256 bytes
 
 
-#ifdef ARM9
 /* DTCM */
 #define DTCM_BASE            (0xFFF00000)
-#define DTCM_SIZE            (0x00004000) // 16 KB
+#define DTCM_SIZE            (0x00004000) // 16 KiB
 
 
 /* ARM9 bootrom */
 #define BOOT9_BASE           (0xFFFF0000)
-#define BOOT9_SIZE           (0x00010000) // 64 KB
+#define BOOT9_SIZE           (0x00010000) // 64 KiB
 #endif
 
 
diff --git a/source/arm11/menu/menu_func.c b/source/arm11/menu/menu_func.c
index 0f59504..e80b28b 100644
--- a/source/arm11/menu/menu_func.c
+++ b/source/arm11/menu/menu_func.c
@@ -924,19 +924,22 @@
 
 	// dump boot9.bin
 	ee_printf("Dumping ARM9 bootrom... ");
-	valid = fsQuickCreate("sdmc:/3DS/boot9.bin", (void*) BOOT9_BASE, BOOT9_SIZE);
+	u8 *dumpPtr = (u8*)VRAM_BASE + VRAM_SIZE - OTP_SIZE - BOOT11_SIZE - BOOT9_SIZE;
+	valid = fsQuickCreate("sdmc:/3DS/boot9.bin", dumpPtr, BOOT9_SIZE);
 	ee_printf(valid ? ESC_SCHEME_GOOD "success\n" ESC_RESET : ESC_SCHEME_BAD "failed!\n" ESC_RESET);
 	updateScreens();
 
 	// dump boot11.bin
 	ee_printf("Dumping ARM11 bootrom... ");
-	valid = fsQuickCreate("sdmc:/3DS/boot11.bin", (void*) (VRAM_BASE + VRAM_SIZE - BOOT11_SIZE), BOOT11_SIZE);
+	dumpPtr += BOOT9_SIZE;
+	valid = fsQuickCreate("sdmc:/3DS/boot11.bin", dumpPtr, BOOT11_SIZE);
 	ee_printf(valid ? ESC_SCHEME_GOOD "success\n" ESC_RESET : ESC_SCHEME_BAD "failed!\n" ESC_RESET);
 	updateScreens();
 
 	// dump otp.bin
 	ee_printf("Dumping OTP... ");
-	valid = fsQuickCreate("sdmc:/3DS/otp.bin", (void*) OTP_BASE, OTP_SIZE);
+	dumpPtr += BOOT11_SIZE;
+	valid = fsQuickCreate("sdmc:/3DS/otp.bin", dumpPtr, OTP_SIZE);
 	ee_printf(valid ? ESC_SCHEME_GOOD "success\n" ESC_RESET : ESC_SCHEME_BAD "failed!\n" ESC_RESET);
 	updateScreens();
 
diff --git a/source/arm11/start.s b/source/arm11/start.s
index 0062004..1d774a4 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -221,8 +221,8 @@
 	mov r2, #1
 	ldr r0, =BOOT11_BASE
 	strb r2, [r1]
-	ldr r1, =VRAM_BASE + VRAM_SIZE - 0x10000
-	mov r2, #0x10000
+	ldr r1, =VRAM_BASE + VRAM_SIZE - 0x100 - BOOT11_SIZE
+	mov r2, #BOOT11_SIZE
 	checkSuperhax_lp:
 		ldmia r0!, {r3-r6}
 		stmia r1!, {r3-r6}
diff --git a/source/arm9/start.s b/source/arm9/start.s
index d0b12f0..bf96c06 100644
--- a/source/arm9/start.s
+++ b/source/arm9/start.s
@@ -17,7 +17,9 @@
  */
 
 #include "arm.h"
+#define ARM11
 #include "mem_map.h"
+#undef ARM11
 
 .arm
 .cpu arm946e-s
@@ -32,6 +34,7 @@
 .type setupExceptionVectors %function
 .type setupTcms %function
 .type clearMem %function
+.type checkSuperhax %function
 .type setupMpu %function
 .type _init %function
 .type deinitCpu %function
@@ -96,13 +99,14 @@
 
 	bl setupMpu
 
+	bl checkSuperhax
 	@ Clear bss section
 	ldr r0, =__bss_start__
 	ldr r1, =__bss_end__
 	sub r1, r1, r0
 	bl clearMem
 	@ Setup newlib heap
-	ldr r0, =IO_MEM_BASE        @ CFG9 regs
+	ldr r0, =IO_MEM_ARM9_ONLY   @ CFG9 regs
 	ldr r1, [r0, #0xFFC]        @ REG_CFG9_MPCORECFG
 	tst r1, #2                  @ Test for New 3DS bit
 	movne r2, #1
@@ -202,6 +206,31 @@
 .pool
 
 
+checkSuperhax:
+	ldr r0, =IO_MEM_ARM9_ONLY @ CFG9 regs
+	ldrb r1, [r0]
+	cmp r1, #0
+	bxne lr
+	ldr r0, =BOOT9_BASE
+	ldr r1, =VRAM_BASE + VRAM_SIZE - OTP_SIZE - BOOT11_SIZE - BOOT9_SIZE
+	ldr r2, =BOOT9_SIZE
+	add r12, r1, #BOOT11_SIZE + BOOT9_SIZE
+	checkSuperhax_lp:
+		ldmia r0!, {r3-r6}
+		stmia r1!, {r3-r6}
+		subs r2, r2, #16
+		bne checkSuperhax_lp
+	cmp r12, #0
+	bxeq lr
+	ldr r0, =OTP_BASE
+	mov r1, r12
+	mov r12, #0
+	ldr r2, =OTP_SIZE
+	b checkSuperhax_lp
+
+.pool
+
+
 #define REGION_4KiB   (0b01011)
 #define REGION_8KiB   (0b01100)
 #define REGION_16KiB  (0b01101)