diff --git a/source/arm11/hardware/interrupt.c b/source/arm11/hardware/interrupt.c
index 0e2e8ba..a55a2a6 100644
--- a/source/arm11/hardware/interrupt.c
+++ b/source/arm11/hardware/interrupt.c
@@ -22,51 +22,47 @@
 #include "arm11/hardware/cfg11.h"
 
 
-IrqHandler irqHandlerTable[224] = {0}; // First 32 interrupts are private to each core (4 * 32).
-                                       // 96 external interrupts (total 128).
+// First 32 interrupts are private to each core (4 * 32).
+// 96 external interrupts (total 128).
+IrqHandler irqHandlerTable[224] = {0};
 
 
 
 void IRQ_init(void)
 {
-	// Disable the interrupt interface for this CPU
-	REG_CPU_II_CNT = 0;
+	REG_CPU_II_CNT = 0; // Disable the interrupt interface for this CPU.
 
-
-	if(!__getCpuId())
+	if(!__getCpuId()) // Core 0
 	{
-		// Disable FIQs
-		REG_CFG11_FIQ_CNT = 1;
+		REG_CFG11_FIQ_CNT = 1; // Disable FIQs.
 
-		// Disable the global interrupt distributor
-		REG_GID_CNT = 0;
+		REG_GID_CNT = 0; // Disable the global interrupt distributor.
 
-		// Disable all 128 interrupts
-		REGs_GID_ENA_CLR[0] = 0xFFFFFFFFu; // Interrupts 0-15 cant be disabled
+		// Disable all 128 interrupts.
+		REGs_GID_ENA_CLR[0] = 0xFFFFFFFFu; // Interrupts 0-15 cant be disabled.
 		REGs_GID_ENA_CLR[1] = 0xFFFFFFFFu;
 		REGs_GID_ENA_CLR[2] = 0xFFFFFFFFu;
 		REGs_GID_ENA_CLR[3] = 0xFFFFFFFFu;
 
-		// Set all pending interrupts to inactive state
-		REGs_GID_PEN_CLR[0] = 0xFFFFFFFFu; // Interrupt 0-15 can't be set to inactive apparently
+		// Set all pending interrupts to inactive state.
+		REGs_GID_PEN_CLR[0] = 0xFFFFFFFFu; // Interrupt 0-15 can't be set to inactive apparently.
 		REGs_GID_PEN_CLR[1] = 0xFFFFFFFFu;
 		REGs_GID_PEN_CLR[2] = 0xFFFFFFFFu;
 		REGs_GID_PEN_CLR[3] = 0xFFFFFFFFu;
 
-		// Set all 128 interrupts to lowest priority
+		// Set all 128 interrupts to lowest priority.
 		for(u32 i = 0; i < 32; i++) REGs_GID_IPRIO[i] = 0xE0E0E0E0u;
 
 		// Set all 128 interrupts to target no CPU.
-		// Interrupt 0-31 can't be changed
+		// Interrupt 0-31 can't be changed.
 		for(u32 i = 8; i < 32; i++) REGs_GID_ITARG[i] = 0;
 
-		// Set all interrupts to rising edge sensitive and 1-N software model
+		// Set all interrupts to rising edge sensitive and 1-N software model.
 		for(u32 i = 0; i < 8; i++) REGs_GID_ICONF[i] = 0xFFFFFFFFu;
 
-		// Enable the global interrupt distributor
-		REG_GID_CNT = 1;
+		REG_GID_CNT = 1; // Enable the global interrupt distributor.
 	}
-	else
+	else // Other core. Same as above but for core specific IRQs.
 	{
 		REGs_GID_PEN_CLR[0] = 0xFFFFFFFFu;
 
@@ -77,14 +73,11 @@
 	}
 
 
-	// Mask no interrupt
-	REG_CPU_II_MASK = 0xF0;
-	// All priority bits are compared for pre-emption
-	REG_CPU_II_BIN_POI = 3;
-	// Enable the interrupt interface for this CPU
-	REG_CPU_II_CNT = 1;
+	REG_CPU_II_MASK = 0xF0; // Mask no interrupt.
+	REG_CPU_II_BIN_POI = 3; // All priority bits are compared for pre-emption.
+	REG_CPU_II_CNT = 1;     // Enable the interrupt interface for this CPU.
 
-	// Get rid of all interrupts stuck in pending/active state
+	// Get rid of all interrupts stuck in pending/active state.
 	u32 tmp;
 	do
 	{
@@ -100,20 +93,24 @@
 
 	const u32 oldState = enterCriticalSection();
 
-	if(handler) irqHandlerTable[(id < 32 ? 32 * cpuId + id : 96u + id)] = handler;
+	irqHandlerTable[(id < 32 ? 32 * cpuId + id : 96u + id)] = handler;
 
+	// Priority
 	u32 shift = (id % 4 * 8) + 4;
 	u32 tmp = REGs_GID_IPRIO[id>>2] & ~(0xFu<<shift);
 	REGs_GID_IPRIO[id>>2] = tmp | (u32)prio<<shift;
 
+	// Target
 	shift = id % 4 * 8;
 	tmp = REGs_GID_ITARG[id>>2] & ~(0xFu<<shift);
 	REGs_GID_ITARG[id>>2] = tmp | (u32)cpuMask<<shift;
 
+	// Trigger level
 	shift = (id % 16 * 2) + 1;
 	tmp = REGs_GID_ICONF[id>>4] & ~(1u<<shift);
 	REGs_GID_ICONF[id>>4] = tmp | (u32)edgeTriggered<<shift;
 
+	// Enable it.
 	REGs_GID_ENA_SET[id>>5] = 1u<<(id % 32);
 
 	leaveCriticalSection(oldState);
@@ -144,7 +141,7 @@
 {
 	const u32 oldState = enterCriticalSection();
 
-	u32 shift = (id % 4 * 8) + 4;
+	const u32 shift = (id % 4 * 8) + 4;
 	u32 tmp = REGs_GID_IPRIO[id>>2] & ~(0xFu<<shift);
 	REGs_GID_IPRIO[id>>2] = tmp | (u32)prio<<shift;