diff --git a/include/arm9/crypto.h b/include/arm9/crypto.h
index 564a181..f97d890 100644
--- a/include/arm9/crypto.h
+++ b/include/arm9/crypto.h
@@ -52,7 +52,7 @@
 #define AES_FLUSH_WRITE_FIFO       (1u<<11)
 #define AES_BIT12                  (1u<<12)
 #define AES_BIT13                  (1u<<13)
-#define AES_MAC_SIZE(n)            ((n - 2 / 2)<<16)
+#define AES_MAC_SIZE(n)            (((n - 2) / 2)<<16)
 #define AES_MAC_REGISTER_SOURCE    (1u<<20)
 #define AES_MAC_STATUS             (1u<<21) // AES_UNKNOWN_21
 #define AES_OUTPUT_BIG             (1u<<22)
diff --git a/source/arm9/crypto.c b/source/arm9/crypto.c
index cca4f40..7e91f45 100644
--- a/source/arm9/crypto.c
+++ b/source/arm9/crypto.c
@@ -64,7 +64,7 @@
 	if(keyslot > 3) // CTR keyslot
 	{
 		REG_AESKEYCNT = keyslot | (useTwlScrambler<<6) | 0x80;
-		for(u32 i = 0; i < 4; i++) REG_AESKEYFIFO[type * 4] = key[i];
+		for(u32 i = 0; i < 4; i++) REG_AESKEYFIFO[type] = key[i];
 	}
 	else // TWL keyslot
 	{
@@ -95,8 +95,7 @@
 		for(u32 i = 0; i < ctrIvNonceSize; i++) ctx->ctrIvNonce[i] = ctrIvNonce[ctrIvNonceSize - 1 - i];
 	}
 	else for(u32 i = 0; i < ctrIvNonceSize; i++) ctx->ctrIvNonce[i] = ctrIvNonce[i];
-
-	ctx->ctrIvNonceEndianess = params & AES_INPUT_BIG; // Mask for input endianess.
+	ctx->ctrIvNonceEndianess = params;
 
 	// If cipher mode is CTR add the initial value to it. Can be 0.
 	if(((params>>27) & 7) == 2) addCounter(ctx->ctrIvNonce, initialCtr);
@@ -136,7 +135,7 @@
 		blockSize = ((size - offset > AES_MAX_BUF_SIZE) ? AES_MAX_BUF_SIZE : size - offset);
 
 		REG_AESBLKCNT = (blockSize>>4)<<16;
-		REG_AESCNT = AES_ENABLE | ctx->aesParams;
+		REG_AESCNT = AES_ENABLE | AES_FLUSH_READ_FIFO | AES_FLUSH_WRITE_FIFO | ctx->aesParams;
 
 		for(u32 j = 0; j < blockSize>>2; j += 4)
 		{
diff --git a/source/arm9/dev.c b/source/arm9/dev.c
index b4ded9b..31b5a9e 100644
--- a/source/arm9/dev.c
+++ b/source/arm9/dev.c
@@ -294,10 +294,10 @@
 		AES_setKey(AES_INPUT_LITTLE | AES_INPUT_REVERSED_ORDER, 3, AES_KEY_TYPE_Y, twlKeyY, false, true);
 
 		// Crypt settings
-		AES_setCryptParams(&dev_dnand.twlAesCtx, AES_FLUSH_READ_FIFO | AES_FLUSH_WRITE_FIFO | AES_BIT12 | AES_BIT13 | AES_OUTPUT_LITTLE |
-							AES_INPUT_LITTLE | AES_OUTPUT_REVERSED_ORDER | AES_INPUT_REVERSED_ORDER | AES_MODE_CTR);
-		AES_setCryptParams(&dev_dnand.ctrAesCtx, AES_FLUSH_READ_FIFO | AES_FLUSH_WRITE_FIFO | AES_BIT12 | AES_BIT13 | AES_OUTPUT_BIG |
-							AES_INPUT_BIG | AES_OUTPUT_NORMAL_ORDER | AES_INPUT_NORMAL_ORDER | AES_MODE_CTR);
+		AES_setCryptParams(&dev_dnand.twlAesCtx, AES_BIT12 | AES_BIT13 | AES_OUTPUT_LITTLE | AES_INPUT_LITTLE |
+							AES_OUTPUT_REVERSED_ORDER | AES_INPUT_REVERSED_ORDER | AES_MODE_CTR);
+		AES_setCryptParams(&dev_dnand.ctrAesCtx, AES_BIT12 | AES_BIT13 | AES_OUTPUT_BIG | AES_INPUT_BIG |
+							AES_OUTPUT_NORMAL_ORDER | AES_INPUT_NORMAL_ORDER | AES_MODE_CTR);
 
 		dev_dnand.dev.initialized = true;
 	}