diff --git a/source/arm11/mmu.c b/source/arm11/mmu.c
index c6a3f9e..72bd224 100644
--- a/source/arm11/mmu.c
+++ b/source/arm11/mmu.c
@@ -82,7 +82,7 @@
 	}
 }
 
-void NAKED setupMmu(void)
+void setupMmu(void)
 {
 	// TTBR0 address shared page table walk and outer cachable write-through, no allocate on write
 	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 0" : : "r" (A11_MMU_TABLES_BASE | 0x12u));
@@ -151,10 +151,9 @@
 	                  // subpage AP bits disabled
 	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0" : : "r" (tmp));
 
-	// Invalidate all caches + Data Synchronization Barrier + return
+	// Invalidate all caches + Data Synchronization Barrier
 	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4\n\t"
 	                     "mcr p15, 0, %0, c7, c5, 0\n\t"
 	                     "mcr p15, 0, %0, c7, c6, 0\n\t"
-	                     "mcr p15, 0, %0, c7, c10, 4\n\t"
-	                     "bx lr" : : "r" (0u));
+	                     "mcr p15, 0, %0, c7, c10, 4" : : "r" (0u));
 }
diff --git a/source/arm11/start.s b/source/arm11/start.s
index af6a6f1..c43374b 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -63,10 +63,10 @@
 	mov r0, #0
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
 
-	mcr p15, 0, r0, c7, c5, 4   @ Flush Prefetch Buffer
-	mcr p15, 0, r0, c7, c5, 0   @ Invalidate Entire Instruction Cache. Also flushes the branch target cache
-	mcr p15, 0, r0, c7, c6, 0   @ Invalidate Entire Data Cache
-	mcr p15, 0, r0, c7, c10, 4  @ Data Synchronization Barrier
+	mcr p15, 0, r0, c7, c5, 4  @ Flush Prefetch Buffer
+	mcr p15, 0, r0, c7, c5, 0  @ Invalidate Entire Instruction Cache. Also flushes the branch target cache
+	mcr p15, 0, r0, c7, c6, 0  @ Invalidate Entire Data Cache
+	mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
 
 	bl stubExceptionVectors     @ Stub the vectors in AXIWRAM bootrom vectors jump to
 
@@ -84,10 +84,10 @@
 	sub r1, r1, r0
 	bl clearMem
 
-	blx setupMmu
+	//blx setupMmu
 	bl setupVfp
 	clrex
-	cpsie a
+	//cpsie a
 
 	blx __libc_init_array      @ Initialize ctors and dtors
 
@@ -184,10 +184,10 @@
 	                            @ and L1 parity checking
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
 
-	mcr p15, 0, r2, c7, c5, 4   @ Flush Prefetch Buffer
-	mcr p15, 0, r2, c7, c5, 0   @ Invalidate Entire Instruction Cache. Also flushes the branch target cache
-	mcr p15, 0, r2, c7, c6, 0   @ Invalidate Entire Data Cache
-	mcr p15, 0, r2, c7, c10, 4  @ Data Synchronization Barrier
+	mcr p15, 0, r2, c7, c5, 4  @ Flush Prefetch Buffer
+	mcr p15, 0, r2, c7, c5, 0  @ Invalidate Entire Instruction Cache. Also flushes the branch target cache
+	mcr p15, 0, r2, c7, c6, 0  @ Invalidate Entire Data Cache
+	mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
 
 	@ Disable VFP11
 	fmxr fpscr, r2              @ Write Floating-Point Status and Control Register