diff --git a/eclipse_project/.cproject b/eclipse_project/.cproject deleted file mode 100644 index 8905299..0000000 --- a/eclipse_project/.cproject +++ /dev/null @@ -1,110 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/eclipse_project/.project b/eclipse_project/.project deleted file mode 100644 index 9589629..0000000 --- a/eclipse_project/.project +++ /dev/null @@ -1,353 +0,0 @@ - - - 3ds_bootloader - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - arm11 - 2 - virtual:/virtual - - - arm9 - 2 - virtual:/virtual - - - cache.h - 1 - PARENT-1-PROJECT_LOC/include/cache.h - - - gfx.h - 1 - PARENT-1-PROJECT_LOC/include/gfx.h - - - hid.c - 1 - PARENT-1-PROJECT_LOC/source/hid.c - - - hid.h - 1 - PARENT-1-PROJECT_LOC/include/hid.h - - - io.h - 1 - PARENT-1-PROJECT_LOC/include/io.h - - - mem_map.h - 1 - PARENT-1-PROJECT_LOC/include/mem_map.h - - - pxi.h - 1 - PARENT-1-PROJECT_LOC/include/pxi.h - - - types.h - 1 - PARENT-1-PROJECT_LOC/include/types.h - - - util.c - 1 - PARENT-1-PROJECT_LOC/source/util.c - - - util.h - 1 - PARENT-1-PROJECT_LOC/include/util.h - - - version.h - 1 - PARENT-1-PROJECT_LOC/include/version.h - - - arm11/cache.s - 1 - PARENT-1-PROJECT_LOC/source/arm11/cache.s - - - arm11/gfx.c - 1 - PARENT-1-PROJECT_LOC/source/arm11/gfx.c - - - arm11/gpio.s - 1 - PARENT-1-PROJECT_LOC/source/arm11/gpio.s - - - arm11/i2c.c - 1 - PARENT-1-PROJECT_LOC/source/arm11/i2c.c - - - arm11/main.c - 1 - PARENT-1-PROJECT_LOC/source/arm11/main.c - - - arm11/pxi.c - 1 - PARENT-1-PROJECT_LOC/source/arm11/pxi.c - - - arm11/start.s - 1 - PARENT-1-PROJECT_LOC/source/arm11/start.s - - - arm9/cache.s - 1 - PARENT-1-PROJECT_LOC/source/arm9/cache.s - - - arm9/config.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/config.h - - - arm9/config_parser.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/config_parser.c - - - arm9/console.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/console.c - - - arm9/console.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/console.h - - - arm9/crypto.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/crypto.c - - - arm9/crypto.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/crypto.h - - - arm9/debug.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/debug.c - - - arm9/dev.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/dev.c - - - arm9/dev.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/dev.h - - - arm9/exception.s - 1 - PARENT-1-PROJECT_LOC/source/arm9/exception.s - - - arm9/fatfs - 2 - virtual:/virtual - - - arm9/filebrowse.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/filebrowse.c - - - arm9/firm.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/firm.c - - - arm9/firm.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/firm.h - - - arm9/gamecard.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/gamecard.c - - - arm9/gamecard.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/gamecard.h - - - arm9/interrupt.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/interrupt.h - - - arm9/main.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/main.c - - - arm9/main.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/main.h - - - arm9/menu.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/menu.c - - - arm9/menu.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/menu.h - - - arm9/ncch.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/ncch.h - - - arm9/ncsd.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/ncsd.h - - - arm9/ndma.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/ndma.c - - - arm9/ndma.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/ndma.h - - - arm9/pxi.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/pxi.c - - - arm9/sdmmc.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/sdmmc.c - - - arm9/sdmmc.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/sdmmc.h - - - arm9/spiflash.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/spiflash.c - - - arm9/spiflash.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/spiflash.h - - - arm9/start.s - 1 - PARENT-1-PROJECT_LOC/source/arm9/start.s - - - arm9/system.s - 1 - PARENT-1-PROJECT_LOC/source/arm9/system.s - - - arm9/systemInit.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/systemInit.c - - - arm9/timer.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/timer.c - - - arm9/timer.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/timer.h - - - arm9/util_nand.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/util_nand.c - - - arm9/util_nand.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/util_nand.h - - - arm9/fatfs/ccsbcs.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/fatfs/ccsbcs.c - - - arm9/fatfs/diskio.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/fatfs/diskio.c - - - arm9/fatfs/diskio.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/fatfs/diskio.h - - - arm9/fatfs/ff.c - 1 - PARENT-1-PROJECT_LOC/source/arm9/fatfs/ff.c - - - arm9/fatfs/ff.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/fatfs/ff.h - - - arm9/fatfs/ffconf.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/fatfs/ffconf.h - - - arm9/fatfs/integer.h - 1 - PARENT-1-PROJECT_LOC/include/arm9/fatfs/integer.h - - - diff --git a/source/arm11/cpu.s b/source/arm11/cpu.s deleted file mode 100644 index 01d4054..0000000 --- a/source/arm11/cpu.s +++ /dev/null @@ -1,122 +0,0 @@ -#include "mem_map.h" - -.arm -.cpu mpcore -.fpu vfpv2 - -.global initCpu -.global deinitCpu - -.type initCpu STT_FUNC -.type stubExceptionVectors STT_FUNC -.type setupVfp STT_FUNC -.type deinitCpu STT_FUNC - -.extern setupMmu -.extern flushDCache - -.section ".init" - - - -initCpu: - mov r10, lr - - @ Control register: - @ [29] Force AP functionality : disabled - @ [28] TEX remap : disabled - @ [27] NMFI bit : normal FIQ behavior - @ [25] CPSR E bit on taking an exception : 0 - @ [23] Extended page table configuration : subpage AP bits enabled - @ [22] Unaligned data access : disabled - @ [15] Disable loading TBIT : disabled - @ [13] Vector select : 0x00000000 - @ [12] Level one instruction cache : disabled - @ [11] Program flow prediction : disabled - @ [7] Endianess : little - @ [2] Level one data cache : disabled - @ [1] Strict data address alignment fault: disabled - @ [0] MMU : disabled - ldr r0, =0x54078 - mcr p15, 0, r0, c1, c0, 0 @ Write control register - mov r0, #0 - mcr p15, 0, r0, c1, c0, 1 @ Write Auxiliary Control Register - - mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer - mcr p15, 0, r0, c7, c7, 0 @ Invalidate Both Caches. Also flushes the branch target cache - mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier - clrex - - bl stubExceptionVectors @ Stub the vectors in AXIWRAM bootrom vectors jump to - - mov sp, #0 @ SVC mode sp (Unused, aborts) - cpsid aif, #0x11 @ FIQ mode - mov sp, #0 @ Not yet - cpsid aif, #0x12 @ IRQ mode - mov sp, #0 @ Not yet - cpsid aif, #0x1F @ System mode - ldr sp, =A11_STACK_END - - blx setupMmu - bl setupVfp - - cpsie a - bx r10 -.pool - - -#define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF)) - -stubExceptionVectors: - ldr r0, =A11_VECTORS_START - mov r1, #6 - ldr r2, =MAKE_BRANCH(0, 0) @ Endless loop - stubExceptionVectors_lp: - str r2, [r0], #8 - subs r1, r1, #1 - bne stubExceptionVectors_lp - bx lr - - -setupVfp: - mov r0, #0 - mov r1, #0xF00000 @ Give full access to cp10/11 in user and privileged mode - mcr p15, 0, r1, c1, c0, 2 @ Write Coprocessor Access Control Register - mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer - mov r1, #0x40000000 @ Clear exception bits and enable VFP11 - mov r2, #0x3C00000 @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode - fmxr fpexc, r1 @ Write Floating-point exception register - fmxr fpscr, r2 @ Write Floating-Point Status and Control Register - bx lr -.pool - - -deinitCpu: - cpsid aif, #0x1F @ System mode - mov r3, lr - - bl stubExceptionVectors - bl flushDCache - mov r2, #0 - mrc p15, 0, r0, c1, c0, 0 @ Read control register - ldr r1, =0x803807 @ Enable MMU, Strict data address alignment fault, D-Cache, - @ Program flow prediction, I-Cache, high exception vectors, - @ subpage AP bits disabled - bic r0, r0, r1 - mcr p15, 0, r0, c1, c0, 0 @ Write control register - mrc p15, 0, r0, c1, c0, 1 @ Read Auxiliary Control Register - bic r0, r0, #0x6F @ Return stack, Dynamic branch prediction, Static branch prediction, - @ Instruction folding, SMP mode: the CPU is taking part in coherency - @ and L1 parity checking - mcr p15, 0, r0, c1, c0, 1 @ Write Auxiliary Control Register - - mcr p15, 0, r2, c7, c5, 4 @ Flush Prefetch Buffer - mcr p15, 0, r2, c7, c7, 0 @ Invalidate Both Caches. Also flushes the branch target cache - mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier - clrex - - @ Disable VFP11 - fmxr fpscr, r2 @ Write Floating-Point Status and Control Register - fmxr fpexc, r2 @ Write Floating-point exception register - bx r3 -.pool diff --git a/source/arm11/start.s b/source/arm11/start.s index fe7cea1..a7cea61 100644 --- a/source/arm11/start.s +++ b/source/arm11/start.s @@ -1,3 +1,5 @@ +#include "mem_map.h" + .arm .cpu mpcore .fpu vfpv2 @@ -5,40 +7,75 @@ .global _start .global clearMem .global _init +.global deinitCpu .type vectors STT_FUNC .type _start STT_FUNC +.type stubExceptionVectors STT_FUNC .type clearMem STT_FUNC +.type setupVfp STT_FUNC .type _init STT_FUNC +.type deinitCpu STT_FUNC -.extern initCpu .extern __bss_start__ .extern __bss_end__ +.extern setupMmu .extern __libc_init_array .extern main -.extern deinitCpu .extern firm_launch .section ".crt0" -_vectors: +vectors: ldr pc, =_start @ Reset vector - ldr pc, =(_vectors + 0x04) @ Undefined instruction vector - ldr pc, =(_vectors + 0x08) @ Software interrupt (SVC) vector - ldr pc, =(_vectors + 0x0C) @ Prefetch abort vector - ldr pc, =(_vectors + 0x10) @ Data abort vector - ldr pc, =(_vectors + 0x14) @ Reserved (unused) vector - ldr pc, =(_vectors + 0x18) @ Interrupt (IRQ) vector - ldr pc, =(_vectors + 0x1C) @ Fast interrupt (FIQ) vector + ldr pc, =(vectors + 0x04) @ Undefined instruction vector + ldr pc, =(vectors + 0x08) @ Software interrupt (SVC) vector + ldr pc, =(vectors + 0x0C) @ Prefetch abort vector + ldr pc, =(vectors + 0x10) @ Data abort vector + ldr pc, =(vectors + 0x14) @ Reserved (unused) vector + ldr pc, =(vectors + 0x18) @ Interrupt (IRQ) vector + ldr pc, =(vectors + 0x1C) @ Fast interrupt (FIQ) vector .pool _start: cpsid aif, #0x13 @ Disable all interrupts, SVC mode - bl initCpu + @ Control register: + @ [29] Force AP functionality : disabled + @ [28] TEX remap : disabled + @ [27] NMFI bit : normal FIQ behavior + @ [25] CPSR E bit on taking an exception : 0 + @ [23] Extended page table configuration : subpage AP bits enabled + @ [22] Unaligned data access : disabled + @ [15] Disable loading TBIT : disabled + @ [13] Vector select : 0x00000000 + @ [12] Level one instruction cache : disabled + @ [11] Program flow prediction : disabled + @ [7] Endianess : little + @ [2] Level one data cache : disabled + @ [1] Strict data address alignment fault: disabled + @ [0] MMU : disabled + ldr r0, =0x54078 + mcr p15, 0, r0, c1, c0, 0 @ Write control register + mov r0, #0 + mcr p15, 0, r0, c1, c0, 1 @ Write Auxiliary Control Register + + mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer + mcr p15, 0, r0, c7, c7, 0 @ Invalidate Both Caches. Also flushes the branch target cache + mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier + + bl stubExceptionVectors @ Stub the vectors in AXIWRAM bootrom vectors jump to + + mov sp, #0 @ SVC mode sp (Unused, aborts) + cpsid aif, #0x11 @ FIQ mode + mov sp, #0 @ Not yet + cpsid aif, #0x12 @ IRQ mode + mov sp, #0 @ Not yet + cpsid aif, #0x1F @ System mode + ldr sp, =A11_STACK_END @ Clear bss section ldr r0, =__bss_start__ @@ -46,18 +83,39 @@ sub r1, r1, r0 bl clearMem + blx setupMmu + bl setupVfp + clrex + cpsie a + blx __libc_init_array @ Initialize ctors and dtors mov r0, #0 @ argc mov r1, #0 @ argv blx main cmp r0, #0 - bne . + bne fail_loop bl deinitCpu b firm_launch + fail_loop: + wfi + b fail_loop .pool +#define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF)) + +stubExceptionVectors: + ldr r0, =A11_VECTORS_START + mov r1, #6 + ldr r2, =MAKE_BRANCH(0, 0) @ Endless loop + stubExceptionVectors_lp: + str r2, [r0], #8 + subs r1, r1, #1 + bne stubExceptionVectors_lp + bx lr + + @ void clearMem(u32 *adr, u32 size) clearMem: mov r2, #0 @@ -88,6 +146,50 @@ .pool +setupVfp: + mov r0, #0 + mov r1, #0xF00000 @ Give full access to cp10/11 in user and privileged mode + mcr p15, 0, r1, c1, c0, 2 @ Write Coprocessor Access Control Register + mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer + mov r1, #0x40000000 @ Clear exception bits and enable VFP11 + mov r2, #0x3C00000 @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode + fmxr fpexc, r1 @ Write Floating-point exception register + fmxr fpscr, r2 @ Write Floating-Point Status and Control Register + bx lr +.pool + + _init: bx lr .pool + + +deinitCpu: + cpsid aif, #0x1F @ System mode + mov r3, lr + + bl stubExceptionVectors + bl flushDCache + mov r2, #0 + mrc p15, 0, r0, c1, c0, 0 @ Read control register + ldr r1, =0x803807 @ Enable MMU, Strict data address alignment fault, D-Cache, + @ Program flow prediction, I-Cache, high exception vectors, + @ subpage AP bits disabled + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 @ Write control register + mrc p15, 0, r0, c1, c0, 1 @ Read Auxiliary Control Register + bic r0, r0, #0x6F @ Return stack, Dynamic branch prediction, Static branch prediction, + @ Instruction folding, SMP mode: the CPU is taking part in coherency + @ and L1 parity checking + mcr p15, 0, r0, c1, c0, 1 @ Write Auxiliary Control Register + + mcr p15, 0, r2, c7, c5, 4 @ Flush Prefetch Buffer + mcr p15, 0, r2, c7, c7, 0 @ Invalidate Both Caches. Also flushes the branch target cache + mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier + + @ Disable VFP11 + fmxr fpscr, r2 @ Write Floating-Point Status and Control Register + fmxr fpexc, r2 @ Write Floating-point exception register + clrex + bx r3 +.pool diff --git a/source/arm9/cpu.s b/source/arm9/cpu.s deleted file mode 100644 index c2f11f6..0000000 --- a/source/arm9/cpu.s +++ /dev/null @@ -1,258 +0,0 @@ -#include "mem_map.h" - -.arm -.cpu arm946e-s -.fpu softvfp - -.global initCpu -.global deinitCpu - -.type initCpu STT_FUNC -.type setupExceptionVectors STT_FUNC -.type setupTcms STT_FUNC -.type setupMpu STT_FUNC -.type deinitCpu STT_FUNC - -.extern undefInstrHandler -.extern prefetchAbortHandler -.extern dataAbortHandler -.extern irqHandler -.extern flushDCache - -.section ".init" - - - -initCpu: - mov r10, lr - - @ Control register: - @ [19] ITCM load mode : disabled - @ [18] ITCM : disabled - @ [17] DTCM load mode : disabled - @ [16] DTCM : disabled - @ [15] Disable loading TBIT : disabled - @ [14] Round-robin replacement: disabled - @ [13] Vector select : 0xFFFF0000 - @ [12] I-Cache : disabled - @ [7] Endianess : little - @ [2] D-Cache : disabled - @ [0] MPU : disabled - ldr r0, =0x2078 - mcr p15, 0, r0, c1, c0, 0 @ Write control register - - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ Invalidate I-Cache - mcr p15, 0, r0, c7, c6, 0 @ Invalidate D-Cache - mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer - - bl setupExceptionVectors @ Setup the vectors in ARM9 mem bootrom vectors jump to - - mov sp, #0 @ SVC mode sp (Unused, aborts) - msr cpsr_cxsf, #0xD2 @ IRQ mode - ldr sp, =(A9_STACK_END - 0x3000) - msr cpsr_cxsf, #0xDF @ System mode - ldr sp, =A9_STACK_END - - bl setupMpu - bl setupTcms @ Setup and enable DTCM and ITCM - - bx r10 -.pool - - -#define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF)) - -setupExceptionVectors: - adr r0, __vectorStubs - mov r1, #A9_VECTORS_START - ldmia r0!, {r2-r9} - stmia r1!, {r2-r9} - ldmia r0, {r2-r5} - stmia r1, {r2-r5} - bx lr -__vectorStubs: - ldr pc, irqHandlerPtr - irqHandlerPtr: .word irqHandler - ldr pc, fiqHandlerPtr - fiqHandlerPtr: .word (A9_VECTORS_START + 0x08) - ldr pc, svcHandlerPtr - svcHandlerPtr: .word (A9_VECTORS_START + 0x10) - ldr pc, undefInstrHandlerPtr - undefInstrHandlerPtr: .word undefInstrHandler - ldr pc, prefetchAbortHandlerPtr - prefetchAbortHandlerPtr: .word prefetchAbortHandler - ldr pc, dataAbortHandlerPtr - dataAbortHandlerPtr: .word dataAbortHandler -.pool - - -setupTcms: - ldr r0, =(DTCM_BASE | 0x0A) @ Base = 0xFFF00000, size = 16 KB - mcr p15, 0, r0, c9, c1, 0 @ Write DTCM region reg - mov r0, #(ITCM_BASE | 0x24) @ Base = 0x00000000, size = 512 KB (32 KB mirrored) - mcr p15, 0, r0, c9, c1, 1 @ Write ITCM region reg - - mrc p15, 0, r0, c1, c0, 0 @ Read control register - orr r0, r0, #0x50000 @ Enable DTCM and ITCM - mcr p15, 0, r0, c1, c0, 0 @ Write control register - bx lr -.pool - - -#define REGION_4KB (0b01011) -#define REGION_8KB (0b01100) -#define REGION_16KB (0b01101) -#define REGION_32KB (0b01110) -#define REGION_64KB (0b01111) -#define REGION_128KB (0b10000) -#define REGION_256KB (0b10001) -#define REGION_512KB (0b10010) -#define REGION_1MB (0b10011) -#define REGION_2MB (0b10100) -#define REGION_4MB (0b10101) -#define REGION_8MB (0b10110) -#define REGION_16MB (0b10111) -#define REGION_32MB (0b11000) -#define REGION_64MB (0b11001) -#define REGION_128MB (0b11010) -#define REGION_256MB (0b11011) -#define REGION_512MB (0b11100) -#define REGION_1GB (0b11101) -#define REGION_2GB (0b11110) -#define REGION_4GB (0b11111) -#define MAKE_REGION(adr, size) ((adr) | ((size)<<1) | 1) - -#define PER_NO_ACC (0) -#define PER_PRIV_RW_USR_NO_ACC (0b0001) -#define PER_PRIV_RW_USR_RO (0b0010) -#define PER_PRIV_RW_USR_RW (0b0011) -#define PER_PRIV_RO_USR_NO_ACC (0b0101) -#define PER_PRIV_RO_USR_RO (0b0110) -#define MAKE_PERMISSIONS(r0, r1, r2, r3, r4, r5, r6, r7) \ - ((r0) | (r1<<4) | (r2<<8) | (r3<<12) | (r4<<16) | (r5<<20) | (r6<<24) | (r7<<28)) - -setupMpu: - @ Region 0: ITCM kernel mirror 32 KB - @ Region 1: ARM9 internal mem 1 MB - @ Region 2: IO region 2 MB covers only ARM9 accessible regs - @ Region 3: VRAM 8MB - @ Region 4: DTCM 16 KB - @ Region 5: - (reserved) - @ Region 6: - (reserved) - @ Region 7: Exception vectors + ARM9 bootrom 32 KB - ldr r0, =MAKE_REGION(ITCM_KERNEL_MIRROR, REGION_32KB) - mcr p15, 0, r0, c6, c0, 0 - ldr r0, =MAKE_REGION(A9_RAM_BASE, REGION_1MB) - mcr p15, 0, r0, c6, c1, 0 - ldr r0, =MAKE_REGION(IO_MEM_ARM9_ONLY, REGION_2MB) - mcr p15, 0, r0, c6, c2, 0 - ldr r0, =MAKE_REGION(VRAM_BASE, REGION_8MB) - mcr p15, 0, r0, c6, c3, 0 - ldr r0, =MAKE_REGION(DTCM_BASE, REGION_16KB) - mcr p15, 0, r0, c6, c4, 0 - mov r0, #0 - mcr p15, 0, r0, c6, c5, 0 - //mov r0, #0 - mcr p15, 0, r0, c6, c6, 0 - ldr r0, =MAKE_REGION(BOOT9_BASE, REGION_32KB) - mcr p15, 0, r0, c6, c7, 0 - - @ Data access permissions: - @ Region 0: User = --, Privileged = RW - @ Region 1: User = --, Privileged = RW - @ Region 2: User = --, Privileged = RW - @ Region 3: User = --, Privileged = RW - @ Region 4: User = --, Privileged = RW - @ Region 5: User = --, Privileged = -- - @ Region 6: User = --, Privileged = -- - @ Region 7: User = --, Privileged = RO - ldr r0, =MAKE_PERMISSIONS(PER_PRIV_RW_USR_NO_ACC, PER_PRIV_RW_USR_NO_ACC, - PER_PRIV_RW_USR_NO_ACC, PER_PRIV_RW_USR_NO_ACC, - PER_PRIV_RW_USR_NO_ACC, PER_NO_ACC, - PER_NO_ACC , PER_PRIV_RO_USR_NO_ACC) - mcr p15, 0, r0, c5, c0, 2 @ Data access permissions - - @ Instruction access permissions: - @ Region 0: User = --, Privileged = RO - @ Region 1: User = --, Privileged = RO - @ Region 2: User = --, Privileged = -- - @ Region 3: User = --, Privileged = -- - @ Region 4: User = --, Privileged = -- - @ Region 5: User = --, Privileged = -- - @ Region 6: User = --, Privileged = -- - @ Region 7: User = --, Privileged = RO - ldr r0, =MAKE_PERMISSIONS(PER_PRIV_RO_USR_NO_ACC, PER_PRIV_RO_USR_NO_ACC, - PER_NO_ACC, PER_NO_ACC, - PER_NO_ACC, PER_NO_ACC, - PER_NO_ACC, PER_PRIV_RO_USR_NO_ACC) - mcr p15, 0, r0, c5, c0, 3 @ Instruction access permissions - - @ Data cachable bits: - @ Region 0 = no - @ Region 1 = yes - @ Region 2 = no <-- Never cache IO regs - @ Region 3 = yes - @ Region 4 = no - @ Region 5 = no - @ Region 6 = no - @ Region 7 = yes - mov r0, #0b10001010 - mcr p15, 0, r0, c2, c0, 0 @ Data cachable bits - - @ Instruction cachable bits: - @ Region 0 = no - @ Region 1 = yes - @ Region 2 = no - @ Region 3 = no - @ Region 4 = no - @ Region 5 = no - @ Region 6 = no - @ Region 7 = yes - mov r0, #0b10000010 - mcr p15, 0, r0, c2, c0, 1 @ Instruction cachable bits - - @ Write bufferable bits: - @ Region 0 = no - @ Region 1 = yes - @ Region 2 = no <-- Never buffer IO regs - @ Region 3 = yes - @ Region 4 = no - @ Region 5 = no - @ Region 6 = no - @ Region 7 = yes - mov r0, #0b10001010 - mcr p15, 0, r0, c3, c0, 0 @ Write bufferable bits - - mrc p15, 0, r0, c1, c0, 0 @ Read control register - ldr r1, =0x1005 @ MPU, D-Cache and I-Cache bitmask - orr r0, r0, r1 @ Enable MPU, D-Cache and I-Cache - mcr p15, 0, r0, c1, c0, 0 @ Write control register - bx lr -.pool - - -deinitCpu: - msr cpsr_cxsf, #0xDF @ System mode - mov r3, lr - - @ Stub vectors to endless loops - mov r0, #A9_RAM_BASE - mov r1, #6 - ldr r2, =MAKE_BRANCH(0, 0) @ Endless loop - deinitCpu_lp: - str r2, [r0], #8 - subs r1, r1, #1 - bne deinitCpu_lp - - bl flushDCache - mov r2, #0 - mrc p15, 0, r0, c1, c0, 0 @ Read control register - ldr r1, =0x1005 @ MPU, D-Cache and I-Cache bitmask - bic r0, r0, r1 @ Disable MPU, D-Cache and I-Cache - mcr p15, 0, r0, c1, c0, 0 @ Write control register - - mcr p15, 0, r2, c7, c5, 0 @ Invalidate I-Cache - mcr p15, 0, r2, c7, c6, 0 @ Invalidate D-Cache - bx r3 -.pool diff --git a/source/arm9/start.s b/source/arm9/start.s index 441e4a9..ac8d67e 100644 --- a/source/arm9/start.s +++ b/source/arm9/start.s @@ -8,35 +8,66 @@ .global _start .global clearMem .global _init +.global deinitCpu .type _start STT_FUNC +.type setupExceptionVectors STT_FUNC +.type setupTcms STT_FUNC .type clearMem STT_FUNC +.type setupMpu STT_FUNC .type _init STT_FUNC +.type deinitCpu STT_FUNC -.extern initCpu -.extern deinitCpu -.extern __libc_init_array -.extern main -.extern firm_launch .extern __bss_start__ .extern __bss_end__ .extern __end__ .extern fake_heap_start .extern fake_heap_end +.extern __libc_init_array +.extern main +.extern firm_launch .section ".crt0" _start: - msr cpsr_cxsf, #0xD3 @ Disable all interrupts, SVC mode + msr cpsr_cxsf, #0xD3 @ Disable all interrupts, SVC mode b skip_pool .string "3DS BOOTLOADER " .word BOOTLOADER_VERSION skip_pool: - bl initCpu + @ Control register: + @ [19] ITCM load mode : disabled + @ [18] ITCM : disabled + @ [17] DTCM load mode : disabled + @ [16] DTCM : disabled + @ [15] Disable loading TBIT : disabled + @ [14] Round-robin replacement: disabled + @ [13] Vector select : 0xFFFF0000 + @ [12] I-Cache : disabled + @ [7] Endianess : little + @ [2] D-Cache : disabled + @ [0] MPU : disabled + ldr r0, =0x2078 + mcr p15, 0, r0, c1, c0, 0 @ Write control register + + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate I-Cache + mcr p15, 0, r0, c7, c6, 0 @ Invalidate D-Cache + mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer + + bl setupExceptionVectors @ Setup the vectors in ARM9 mem bootrom vectors jump to + + mov sp, #0 @ SVC mode sp (Unused, aborts) + msr cpsr_cxsf, #0xD2 @ IRQ mode + ldr sp, =(A9_STACK_END - 0x3000) + msr cpsr_cxsf, #0xDF @ System mode + ldr sp, =A9_STACK_END + + bl setupTcms @ Setup and enable DTCM and ITCM @ Clear bss section ldr r0, =__bss_start__ @@ -44,6 +75,8 @@ sub r1, r1, r0 bl clearMem + bl setupMpu + @ Setup newlib heap ldr r0, =(__end__ + 12) @ Do not overwrite the value at symbol __end__ bic r0, r0, #7 @ Align to 8 bytes @@ -59,9 +92,53 @@ mov r1, #0 @ argv blx main cmp r0, #0 - bne . + bne fail_loop bl deinitCpu b firm_launch + fail_loop: + mov r0, #0 + @ Wait for interrupt + mcr p15, 0, r0, c7, c0, 4 + b fail_loop +.pool + + +#define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF)) + +setupExceptionVectors: + adr r0, vectorStubs + mov r1, #A9_VECTORS_START + ldmia r0!, {r2-r9} + stmia r1!, {r2-r9} + ldmia r0, {r2-r5} + stmia r1, {r2-r5} + bx lr +vectorStubs: + ldr pc, irqHandlerPtr + irqHandlerPtr: .word irqHandler + ldr pc, fiqHandlerPtr + fiqHandlerPtr: .word (A9_VECTORS_START + 0x08) + ldr pc, svcHandlerPtr + svcHandlerPtr: .word (A9_VECTORS_START + 0x10) + ldr pc, undefInstrHandlerPtr + undefInstrHandlerPtr: .word undefInstrHandler + ldr pc, prefetchAbortHandlerPtr + prefetchAbortHandlerPtr: .word prefetchAbortHandler + ldr pc, dataAbortHandlerPtr + dataAbortHandlerPtr: .word dataAbortHandler +.pool + + +setupTcms: + ldr r0, =(DTCM_BASE | 0x0A) @ Base = 0xFFF00000, size = 16 KB + mcr p15, 0, r0, c9, c1, 0 @ Write DTCM region reg + mov r0, #(ITCM_BASE | 0x24) @ Base = 0x00000000, size = 512 KB (32 KB mirrored) + mcr p15, 0, r0, c9, c1, 1 @ Write ITCM region reg + + mrc p15, 0, r0, c1, c0, 0 @ Read control register + orr r0, r0, #0x50000 @ Enable DTCM and ITCM + mcr p15, 0, r0, c1, c0, 0 @ Write control register + bx lr .pool @@ -95,7 +172,165 @@ .pool +#define REGION_4KB (0b01011) +#define REGION_8KB (0b01100) +#define REGION_16KB (0b01101) +#define REGION_32KB (0b01110) +#define REGION_64KB (0b01111) +#define REGION_128KB (0b10000) +#define REGION_256KB (0b10001) +#define REGION_512KB (0b10010) +#define REGION_1MB (0b10011) +#define REGION_2MB (0b10100) +#define REGION_4MB (0b10101) +#define REGION_8MB (0b10110) +#define REGION_16MB (0b10111) +#define REGION_32MB (0b11000) +#define REGION_64MB (0b11001) +#define REGION_128MB (0b11010) +#define REGION_256MB (0b11011) +#define REGION_512MB (0b11100) +#define REGION_1GB (0b11101) +#define REGION_2GB (0b11110) +#define REGION_4GB (0b11111) +#define MAKE_REGION(adr, size) ((adr) | ((size)<<1) | 1) + +#define PER_NO_ACC (0) +#define PER_PRIV_RW_USR_NO_ACC (0b0001) +#define PER_PRIV_RW_USR_RO (0b0010) +#define PER_PRIV_RW_USR_RW (0b0011) +#define PER_PRIV_RO_USR_NO_ACC (0b0101) +#define PER_PRIV_RO_USR_RO (0b0110) +#define MAKE_PERMISSIONS(r0, r1, r2, r3, r4, r5, r6, r7) \ + ((r0) | (r1<<4) | (r2<<8) | (r3<<12) | (r4<<16) | (r5<<20) | (r6<<24) | (r7<<28)) + +setupMpu: + @ Region 0: ITCM kernel mirror 32 KB + @ Region 1: ARM9 internal mem 1 MB + @ Region 2: IO region 2 MB covers only ARM9 accessible regs + @ Region 3: VRAM 8MB + @ Region 4: DTCM 16 KB + @ Region 5: - (reserved) + @ Region 6: - (reserved) + @ Region 7: Exception vectors + ARM9 bootrom 32 KB + ldr r0, =MAKE_REGION(ITCM_KERNEL_MIRROR, REGION_32KB) + mcr p15, 0, r0, c6, c0, 0 + ldr r0, =MAKE_REGION(A9_RAM_BASE, REGION_1MB) + mcr p15, 0, r0, c6, c1, 0 + ldr r0, =MAKE_REGION(IO_MEM_ARM9_ONLY, REGION_2MB) + mcr p15, 0, r0, c6, c2, 0 + ldr r0, =MAKE_REGION(VRAM_BASE, REGION_8MB) + mcr p15, 0, r0, c6, c3, 0 + ldr r0, =MAKE_REGION(DTCM_BASE, REGION_16KB) + mcr p15, 0, r0, c6, c4, 0 + mov r0, #0 + mcr p15, 0, r0, c6, c5, 0 + //mov r0, #0 + mcr p15, 0, r0, c6, c6, 0 + ldr r0, =MAKE_REGION(BOOT9_BASE, REGION_32KB) + mcr p15, 0, r0, c6, c7, 0 + + @ Data access permissions: + @ Region 0: User = --, Privileged = RW + @ Region 1: User = --, Privileged = RW + @ Region 2: User = --, Privileged = RW + @ Region 3: User = --, Privileged = RW + @ Region 4: User = --, Privileged = RW + @ Region 5: User = --, Privileged = -- + @ Region 6: User = --, Privileged = -- + @ Region 7: User = --, Privileged = RO + ldr r0, =MAKE_PERMISSIONS(PER_PRIV_RW_USR_NO_ACC, PER_PRIV_RW_USR_NO_ACC, + PER_PRIV_RW_USR_NO_ACC, PER_PRIV_RW_USR_NO_ACC, + PER_PRIV_RW_USR_NO_ACC, PER_NO_ACC, + PER_NO_ACC , PER_PRIV_RO_USR_NO_ACC) + mcr p15, 0, r0, c5, c0, 2 @ Data access permissions + + @ Instruction access permissions: + @ Region 0: User = --, Privileged = RO + @ Region 1: User = --, Privileged = RO + @ Region 2: User = --, Privileged = -- + @ Region 3: User = --, Privileged = -- + @ Region 4: User = --, Privileged = -- + @ Region 5: User = --, Privileged = -- + @ Region 6: User = --, Privileged = -- + @ Region 7: User = --, Privileged = RO + ldr r0, =MAKE_PERMISSIONS(PER_PRIV_RO_USR_NO_ACC, PER_PRIV_RO_USR_NO_ACC, + PER_NO_ACC, PER_NO_ACC, + PER_NO_ACC, PER_NO_ACC, + PER_NO_ACC, PER_PRIV_RO_USR_NO_ACC) + mcr p15, 0, r0, c5, c0, 3 @ Instruction access permissions + + @ Data cachable bits: + @ Region 0 = no + @ Region 1 = yes + @ Region 2 = no <-- Never cache IO regs + @ Region 3 = yes + @ Region 4 = no + @ Region 5 = no + @ Region 6 = no + @ Region 7 = yes + mov r0, #0b10001010 + mcr p15, 0, r0, c2, c0, 0 @ Data cachable bits + + @ Instruction cachable bits: + @ Region 0 = no + @ Region 1 = yes + @ Region 2 = no + @ Region 3 = no + @ Region 4 = no + @ Region 5 = no + @ Region 6 = no + @ Region 7 = yes + mov r0, #0b10000010 + mcr p15, 0, r0, c2, c0, 1 @ Instruction cachable bits + + @ Write bufferable bits: + @ Region 0 = no + @ Region 1 = yes + @ Region 2 = no <-- Never buffer IO regs + @ Region 3 = yes + @ Region 4 = no + @ Region 5 = no + @ Region 6 = no + @ Region 7 = yes + mov r0, #0b10001010 + mcr p15, 0, r0, c3, c0, 0 @ Write bufferable bits + + mrc p15, 0, r0, c1, c0, 0 @ Read control register + ldr r1, =0x1005 @ MPU, D-Cache and I-Cache bitmask + orr r0, r0, r1 @ Enable MPU, D-Cache and I-Cache + mcr p15, 0, r0, c1, c0, 0 @ Write control register + bx lr +.pool + + @ Needed by libc _init: bx lr .pool + + +deinitCpu: + msr cpsr_cxsf, #0xDF @ System mode + mov r3, lr + + @ Stub vectors to endless loops + mov r0, #A9_RAM_BASE + mov r1, #6 + ldr r2, =MAKE_BRANCH(0, 0) @ Endless loop + deinitCpu_lp: + str r2, [r0], #8 + subs r1, r1, #1 + bne deinitCpu_lp + + bl flushDCache + mov r2, #0 + mrc p15, 0, r0, c1, c0, 0 @ Read control register + ldr r1, =0x1005 @ MPU, D-Cache and I-Cache bitmask + bic r0, r0, r1 @ Disable MPU, D-Cache and I-Cache + mcr p15, 0, r0, c1, c0, 0 @ Write control register + + mcr p15, 0, r2, c7, c5, 0 @ Invalidate I-Cache + mcr p15, 0, r2, c7, c6, 0 @ Invalidate D-Cache + bx r3 +.pool