diff --git a/include/hardware/pxi.h b/include/hardware/pxi.h index 9dedec6..a75dc88 100644 --- a/include/hardware/pxi.h +++ b/include/hardware/pxi.h @@ -27,17 +27,22 @@ #elif ARM11 #define PXI_REGS_BASE (IO_MEM_ARM9_ARM11 + 0x63000) #endif +#define REG_PXI_DATA_RECEIVED *((vu8 *)(PXI_REGS_BASE + 0x00)) +#define REG_PXI_DATA_SENT *((vu8 *)(PXI_REGS_BASE + 0x01)) #define REG_PXI_SYNC *((vu32*)(PXI_REGS_BASE + 0x00)) -#define REG_PXI_CNT *((vu32*)(PXI_REGS_BASE + 0x04)) +#define REG_PXI_CNT *((vu16*)(PXI_REGS_BASE + 0x04)) #define REG_PXI_SEND *((vu32*)(PXI_REGS_BASE + 0x08)) #define REG_PXI_RECV *((vu32*)(PXI_REGS_BASE + 0x0C)) // Defines for PX_SYNC regs -#define PXI_DATA_RECEIVED(reg) ((reg) & 0xFFu) -#define PXI_DATA_SENT(reg, sent) (((reg) & ~(0xFFu<<8)) | sent<<8) -#define PXI_NOTIFY_11 (1u<<29) -#define PXI_NOTIFY_9 (1u<<30) +#define PXI_DATA_RECEIVED (REG_PXI_SYNC & 0xFFu) +#define PXI_DATA_SENT(sent) ((REG_PXI_SYNC & ~(0xFFu<<8)) | sent<<8) +#ifdef ARM9 +#define PXI_TRIGGER_SYNC_IRQ (1u<<29) +#elif ARM11 +#define PXI_TRIGGER_SYNC_IRQ (1u<<30) +#endif #define PXI_IRQ_ENABLE (1u<<31) // Defines for PXI_CNT regs diff --git a/include/ipc_handler.h b/include/ipc_handler.h index 8ba27b1..2f9cf0f 100644 --- a/include/ipc_handler.h +++ b/include/ipc_handler.h @@ -21,7 +21,7 @@ #include "types.h" -#define IPC_MAX_PARAMS (16) +#define IPC_MAX_PARAMS (15) #define IPC_CMD_ID_MASK(cmd) ((cmd)>>24) #define IPC_CMD_IN_BUFS_MASK(cmd) ((cmd)>>20 & 0xFu) #define IPC_CMD_OUT_BUFS_MASK(cmd) ((cmd)>>26 & 0xFu) diff --git a/source/arm11/main.c b/source/arm11/main.c index ea464be..f7c5591 100644 --- a/source/arm11/main.c +++ b/source/arm11/main.c @@ -29,6 +29,7 @@ #include "arm11/menu_fb3ds.h" #include "arm11/console.h" #include "arm11/fmt.h" + #include "fs.h" volatile bool g_poweroffAllowed = false; diff --git a/source/hardware/pxi.c b/source/hardware/pxi.c index f9d91a4..34ccf1f 100644 --- a/source/hardware/pxi.c +++ b/source/hardware/pxi.c @@ -41,16 +41,16 @@ void PXI_init(void) { REG_PXI_SYNC = PXI_IRQ_ENABLE; - REG_PXI_CNT = PXI_FLUSH_SEND_FIFO | PXI_EMPTY_FULL_ERROR | PXI_ENABLE_SEND_RECV_FIFO; + REG_PXI_CNT = PXI_ENABLE_SEND_RECV_FIFO | PXI_EMPTY_FULL_ERROR | PXI_FLUSH_SEND_FIFO; #ifdef ARM9 - REG_PXI_SYNC |= 9u<<8; - while(PXI_DATA_RECEIVED(REG_PXI_SYNC) != 11u); + REG_PXI_DATA_SENT = 9; + while(REG_PXI_DATA_RECEIVED != 11); IRQ_registerHandler(IRQ_PXI_SYNC, pxiIrqHandler); #elif ARM11 - while(PXI_DATA_RECEIVED(REG_PXI_SYNC) != 9u); - REG_PXI_SYNC |= 11u<<8; + while(REG_PXI_DATA_RECEIVED != 9); + REG_PXI_DATA_SENT = 11; IRQ_registerHandler(IRQ_PXI_SYNC, 13, 0, true, pxiIrqHandler); #endif @@ -64,14 +64,14 @@ const u8 params = IPC_CMD_PARAMS_MASK(cmdCode); const u32 cmdBufSize = ((u32)inBufs * 2) + ((u32)outBufs * 2) + params; - if(cmdBufSize > IPC_MAX_PARAMS || cmdBufSize != PXI_DATA_RECEIVED(REG_PXI_SYNC)) + if(cmdBufSize > IPC_MAX_PARAMS || cmdBufSize != REG_PXI_DATA_RECEIVED) { panic(); } u32 buf[IPC_MAX_PARAMS]; for(u32 i = 0; i < cmdBufSize; i++) buf[i] = REG_PXI_RECV; - if(REG_PXI_SYNC & PXI_EMPTY_FULL_ERROR) panic(); + if(REG_PXI_CNT & PXI_EMPTY_FULL_ERROR) panic(); REG_PXI_SEND = IPC_handleCmd(IPC_CMD_ID_MASK(cmdCode), inBufs, outBufs, buf); } @@ -81,6 +81,7 @@ fb_assert(buf != NULL); fb_assert(words <= IPC_MAX_PARAMS); + const u8 inBufs = IPC_CMD_IN_BUFS_MASK(cmd); const u8 outBufs = IPC_CMD_OUT_BUFS_MASK(cmd); for(u32 i = 0; i < inBufs; i++) @@ -97,13 +98,9 @@ while(REG_PXI_CNT & PXI_SEND_FIFO_FULL); REG_PXI_SEND = cmd; for(u32 i = 0; i < words; i++) REG_PXI_SEND = buf[i]; - if(REG_PXI_SYNC & PXI_EMPTY_FULL_ERROR) panic(); + if(REG_PXI_CNT & PXI_EMPTY_FULL_ERROR) panic(); -#ifdef ARM9 - REG_PXI_SYNC = PXI_DATA_SENT(REG_PXI_SYNC, words) | PXI_NOTIFY_11; -#elif ARM11 - REG_PXI_SYNC = PXI_DATA_SENT(REG_PXI_SYNC, words) | PXI_NOTIFY_9; -#endif + REG_PXI_SYNC = PXI_DATA_SENT(words) | PXI_TRIGGER_SYNC_IRQ; while(REG_PXI_CNT & PXI_RECV_FIFO_EMPTY); return REG_PXI_RECV;