diff --git a/include/cache.h b/include/cache.h
index 0ceeeb9..c755158 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -5,10 +5,8 @@
 
 
 void invalidateICache(void);
+void invalidateICacheRange(void *base, u32 size);
 void flushDCache(void);
-#ifdef ARM9
-void invalidateICacheRange(const void *base, u32 size);
-void flushDCacheRange(const void *base, u32 size);
+void flushDCacheRange(void *base, u32 size);
 void invalidateDCache(void);
-void invalidateDCacheRange(const void *base, u32 size);
-#endif
+void invalidateDCacheRange(void *base, u32 size);
diff --git a/source/arm11/cache.s b/source/arm11/cache.s
index c124530..fb44102 100644
--- a/source/arm11/cache.s
+++ b/source/arm11/cache.s
@@ -3,28 +3,89 @@
 .fpu vfpv2
 
 .global invalidateICache
+.global invalidateICacheRange
 .global flushDCache
+.global flushDCacheRange
+.global invalidateDCache
+.global invalidateDCacheRange
 
 .type invalidateICache STT_FUNC
+.type invalidateICacheRange STT_FUNC
 .type flushDCache STT_FUNC
+.type flushDCacheRange STT_FUNC
+.type invalidateDCache STT_FUNC
+.type invalidateDCacheRange STT_FUNC
 
 .section ".text"
 
 
+#define CACHE_LINE_SIZE	(32)
+
+
 
 invalidateICache:
-	@ Invalidate Entire Instruction Cache,
-	@ also flushes the branch target cache
 	mov r0, #0
-	mcr p15, 0, r0, c7, c5, 0
-	mcr p15, 0, r0, c7, c5, 4  @ Flush Prefetch Buffer
-	mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
+	mcr p15, 0, r0, c7, c5, 0       @ Invalidate Entire Instruction Cache, also flushes the branch target cache
+	@mcr p15, 0, r0, c7, c5, 6       @ Flush Entire Branch Target Cache
+	mcr p15, 0, r0, c7, c10, 4      @ Data Synchronization Barrier
+	mcr p15, 0, r0, c7, c5, 4       @ Flush Prefetch Buffer
 	bx lr
 
 
+invalidateICacheRange:
+	add	r1, r1, r0
+	bic	r0, r0, #(CACHE_LINE_SIZE - 1)
+	mov r2, #0
+invalidateICacheRange_lp:
+	mcr	p15, 0, r0, c7, c5, 1       @ Invalidate Instruction Cache Line (using MVA)
+	add	r0, r0, #CACHE_LINE_SIZE
+	cmp	r0, r1
+	blt	invalidateICacheRange_lp
+	mcr p15, 0, r2, c7, c5, 6       @ Flush Entire Branch Target Cache
+	mcr p15, 0, r2, c7, c10, 4      @ Data Synchronization Barrier
+	mcr p15, 0, r2, c7, c5, 4       @ Flush Prefetch Buffer
+	bx	lr
+
+
 flushDCache:
-	@ Clear and Invalidate Entire Data Cache
 	mov r0, #0
-	mcr p15, 0, r0, c7, c14, 0
-	mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
+	mcr p15, 0, r0, c7, c10, 0      @ "Clean Entire Data Cache"
+	mcr p15, 0, r0, c7, c10, 4      @ Data Synchronization Barrier
 	bx lr
+
+
+flushDCacheRange:
+	add	r1, r1, r0
+	bic	r0, r0, #(CACHE_LINE_SIZE - 1)
+	mov r2, #0
+flushDCacheRange_lp:
+	mcr p15, 0, r0, c7, c10, 1      @ "Clean Data Cache Line (using MVA)"
+	add	r0, r0, #CACHE_LINE_SIZE
+	cmp	r0, r1
+	blt	flushDCacheRange_lp
+	mcr p15, 0, r2, c7, c10, 4      @ Data Synchronization Barrier
+	bx lr
+
+
+invalidateDCache:
+	mov	r0, #0
+	mcr p15, 0, r0, c7, c6, 0       @ Invalidate Entire Data Cache
+	mcr p15, 0, r0, c7, c10, 4      @ Data Synchronization Barrier
+	bx  lr
+
+
+invalidateDCacheRange:
+	add	r1, r1, r0
+	tst	r0, #(CACHE_LINE_SIZE - 1)
+	mcrne   p15, 0, r0, c7, c10, 1  @ "Clean Data Cache Line (using MVA)"
+	tst	r1, #(CACHE_LINE_SIZE - 1)
+	mcrne   p15, 0, r1, c7, c10, 1  @ "Clean Data Cache Line (using MVA)"
+	bic	r0, r0, #(CACHE_LINE_SIZE - 1)
+	mov r2, #0
+invalidateDCacheRange_lp:
+	mcr	p15, 0, r0, c7, c6, 1       @ Invalidate Data Cache Line (using MVA)
+	add	r0, r0, #CACHE_LINE_SIZE
+	cmp	r0, r1
+	blt	invalidateDCacheRange_lp
+	mcr p15, 0, r2, c7, c10, 4      @ Data Synchronization Barrier
+	bx  lr
diff --git a/source/arm9/cache.s b/source/arm9/cache.s
index b04d8dc..ed29f93 100644
--- a/source/arm9/cache.s
+++ b/source/arm9/cache.s
@@ -27,68 +27,68 @@
 
 invalidateICache:
 	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 0
+	mcr	p15, 0, r0, c7, c5, 0       @ "Flush instruction cache"
 	bx	lr
 
 
 invalidateICacheRange:
 	add	r1, r1, r0
 	bic	r0, r0, #(CACHE_LINE_SIZE - 1)
-invalidateI:
-	mcr	p15, 0, r0, c7, c5, 1
+invalidateICacheRange_lp:
+	mcr	p15, 0, r0, c7, c5, 1       @ "Flush instruction cache single entry Address"
 	add	r0, r0, #CACHE_LINE_SIZE
 	cmp	r0, r1
-	blt	invalidateI
+	blt	invalidateICacheRange_lp
 	bx	lr
 
 
 flushDCache:
 	mov	r1, #0
-outer_loop:
+flushDCache_outer_lp:
 	mov	r0, #0
-inner_loop:
-	orr	r2, r1, r0              @ Generate segment and line address
-	mcr	p15, 0, r2, c7, c14, 2  @ Clean and flush the line
+flushDCache_inner_lp:
+	orr	r2, r1, r0                   @ Generate segment and line address
+	mcr	p15, 0, r2, c7, c10, 2       @ "Clean data cache entry Index and segment"
 	add	r0, r0, #CACHE_LINE_SIZE
 	cmp	r0, #(DCACHE_SIZE / 4)
-	bne	inner_loop
+	bne	flushDCache_inner_lp
 	add	r1, r1, #0x40000000
 	cmp	r1, #0
-	bne	outer_loop
+	bne	flushDCache_outer_lp
 	b   drainWriteBuffer
 
 
 flushDCacheRange:
 	add	r1, r1, r0
 	bic	r0, r0, #(CACHE_LINE_SIZE - 1)
-flush:
-	mcr	p15, 0, r0, c7, c14, 1  @ Clean and flush address
+flushDCacheRange_lp:
+	mcr	p15, 0, r0, c7, c10, 1      @ "Clean data cache entry Address"
 	add	r0, r0, #CACHE_LINE_SIZE
 	cmp	r0, r1
-	blt	flush
+	blt	flushDCacheRange_lp
 
 drainWriteBuffer:
 	mov r0, #0
-	mcr p15, 0, r0, c7, c10, 4  @ Drain write buffer
+	mcr p15, 0, r0, c7, c10, 4      @ Drain write buffer
 	bx  lr
 
 
 invalidateDCache:
 	mov	r0, #0
-	mcr	p15, 0, r0, c7, c6, 0
+	mcr	p15, 0, r0, c7, c6, 0       @ "Flush data cache"
 	bx  lr
 
 
 invalidateDCacheRange:
 	add	r1, r1, r0
 	tst	r0, #(CACHE_LINE_SIZE - 1)
-	mcrne   p15, 0, r0, c7, c10, 1  @ Clean D entry
+	mcrne   p15, 0, r0, c7, c10, 1  @ "Clean data cache entry Address"
 	tst	r1, #(CACHE_LINE_SIZE - 1)
-	mcrne   p15, 0, r1, c7, c10, 1  @ Clean D entry
+	mcrne   p15, 0, r1, c7, c10, 1  @ "Clean data cache entry Address"
 	bic	r0, r0, #(CACHE_LINE_SIZE - 1)
-invalidateD:
-	mcr	p15, 0, r0, c7, c6, 1
+invalidateDCacheRange_lp:
+	mcr	p15, 0, r0, c7, c6, 1       @ "Flush data cache single entry Address"
 	add	r0, r0, #CACHE_LINE_SIZE
 	cmp	r0, r1
-	blt	invalidateD
+	blt	invalidateDCacheRange_lp
 	bx  lr