diff --git a/Makefile b/Makefile
index 71a0bef..66eb52f 100644
--- a/Makefile
+++ b/Makefile
@@ -12,4 +12,4 @@
 code11.bin:
 	make -f Makefile.arm11
 firm.bin:
-	firm_builder firm.bin 0x08000040 0x1FF85040 0x08000040 0 code9.bin 0x1FF85000 1 code11.bin
+	firm_builder firm.bin 0x08000054 0x1FF85040 0x08000040 0 code9.bin 0x1FF85000 1 code11.bin
diff --git a/source/arm11/mmu.c b/source/arm11/mmu.c
index 72bd224..24ecde8 100644
--- a/source/arm11/mmu.c
+++ b/source/arm11/mmu.c
@@ -153,7 +153,6 @@
 
 	// Invalidate all caches + Data Synchronization Barrier
 	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4\n\t"
-	                     "mcr p15, 0, %0, c7, c5, 0\n\t"
-	                     "mcr p15, 0, %0, c7, c6, 0\n\t"
+	                     "mcr p15, 0, %0, c7, c7, 0\n\t"
 	                     "mcr p15, 0, %0, c7, c10, 4" : : "r" (0u));
 }
diff --git a/source/arm11/start.s b/source/arm11/start.s
index 4995f4b..e7bf51c 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -27,6 +27,7 @@
 
 
 
+__start__:
 vectors:
 	ldr pc, =_start            @ Reset vector
 	ldr pc, =(vectors + 0x04)  @ Undefined instruction vector
@@ -63,8 +64,7 @@
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
 
 	mcr p15, 0, r0, c7, c5, 4  @ Flush Prefetch Buffer
-	mcr p15, 0, r0, c7, c5, 0  @ Invalidate Entire Instruction Cache. Also flushes the branch target cache
-	mcr p15, 0, r0, c7, c6, 0  @ Invalidate Entire Data Cache
+	mcr p15, 0, r0, c7, c7, 0  @ Invalidate Both Caches. Also flushes the branch target cache
 	mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
 	clrex
 
@@ -179,10 +179,9 @@
 	                            @ and L1 parity checking
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
 
-	mcr p15, 0, r2, c7, c5, 4  @ Flush Prefetch Buffer
-	mcr p15, 0, r2, c7, c5, 0  @ Invalidate Entire Instruction Cache. Also flushes the branch target cache
-	mcr p15, 0, r2, c7, c6, 0  @ Invalidate Entire Data Cache
-	mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
+	mcr p15, 0, r0, c7, c5, 4  @ Flush Prefetch Buffer
+	mcr p15, 0, r0, c7, c7, 0  @ Invalidate Both Caches. Also flushes the branch target cache
+	mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
 
 	@ Disable VFP11
 	fmxr fpscr, r2              @ Write Floating-Point Status and Control Register
diff --git a/source/arm9/menu_update.c b/source/arm9/menu_update.c
index 7a0a5c1..ba546f2 100644
--- a/source/arm9/menu_update.c
+++ b/source/arm9/menu_update.c
@@ -56,14 +56,14 @@
 	}
 	
 	// verify fastboot magic
-	if(memcmp((void*)updateBuffer+0x208, "FASTBOOT 3DS   ", 0x10) != 0)
+	if(memcmp((void*)updateBuffer+0x200, "FASTBOOT 3DS   ", 0x10) != 0)
 	{
 		uiPrintError("Not an update file!\n");
 		goto fail;
 	}
 	
 	/* check version */
-	u32 updateVersion = *(u32 *)((void*)updateBuffer + 0x218);
+	u32 updateVersion = *(u32 *)((void*)updateBuffer + 0x210);
 	
 	if(updateVersion < BOOTLOADER_VERSION)
 	{
diff --git a/source/arm9/start.s b/source/arm9/start.s
index 75e3cae..0725728 100644
--- a/source/arm9/start.s
+++ b/source/arm9/start.s
@@ -30,14 +30,13 @@
 
 
 
-_start:
-	msr cpsr_cxsf, #0xD3         @ Disable all interrupts, SVC mode
-	b skip_pool
-
+__start__:
 	.string "FASTBOOT 3DS   "
 	.word   BOOTLOADER_VERSION
 
-skip_pool:
+_start:
+	msr cpsr_cxsf, #0xD3         @ Disable all interrupts, SVC mode
+
 	@ Control register:
 	@ [19] ITCM load mode         : disabled
 	@ [18] ITCM                   : disabled