diff --git a/source/arm11/hardware/cache.s b/source/arm11/hardware/cache.s
index 82dadf4..5c4b81c 100644
--- a/source/arm11/hardware/cache.s
+++ b/source/arm11/hardware/cache.s
@@ -113,3 +113,6 @@
 		blt invalidateDCacheRange_lp
 	mcr p15, 0, r2, c7, c10, 4      @ Data Synchronization Barrier
 	bx lr
+
+
+.pool
diff --git a/source/arm11/hardware/exception.s b/source/arm11/hardware/exception.s
index d24a2a7..4cddfd3 100644
--- a/source/arm11/hardware/exception.s
+++ b/source/arm11/hardware/exception.s
@@ -90,3 +90,6 @@
 	str r0, [r12, #0x110]        @ REG_CPU_II_EOI
 	ldmfd sp!, {r0-r3, r12, lr}
 	rfefd sp!                    @ Restore lr (pc) and spsr (cpsr)
+
+
+.pool
diff --git a/source/arm11/lz11.s b/source/arm11/lz11.s
index fcc568b..e580b3b 100644
--- a/source/arm11/lz11.s
+++ b/source/arm11/lz11.s
@@ -88,3 +88,6 @@
 	sub    r2, r2, #1          @ size--
 	strb   r4, [r1], #1        @ *out++ = r4
 	b      .Lloop              @ goto loop
+
+
+.pool
diff --git a/source/arm11/start.s b/source/arm11/start.s
index 6f73ff6..a050752 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -156,12 +156,6 @@
 	_start_lp:
 		wfi
 		b _start_lp
-.pool
-_sysmode_stacks:
-	.word A11_C0_STACK_END      @ Stack for core 0
-	.word A11_C1_STACK_END      @ Stack for core 1
-	.word 0                     @ New 3DS cores are not used at all
-	.word 0
 
 
 #define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF))
@@ -175,7 +169,6 @@
 		subs r1, r1, #1
 		bne stubExceptionVectors_lp
 	bx lr
-.pool
 
 
 @ void clearMem(u32 *adr, u32 size)
@@ -250,4 +243,11 @@
 	mcr p15, 0, r2, c7, c7, 0  @ Invalidate Both Caches. Also flushes the branch target cache
 	mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
 	bx r3
+
+
 .pool
+_sysmode_stacks:
+	.word A11_C0_STACK_END      @ Stack for core 0
+	.word A11_C1_STACK_END      @ Stack for core 1
+	.word 0                     @ New 3DS cores are not used at all
+	.word 0
diff --git a/source/arm9/hardware/cache.s b/source/arm9/hardware/cache.s
index 594cfdf..3667e24 100644
--- a/source/arm9/hardware/cache.s
+++ b/source/arm9/hardware/cache.s
@@ -124,3 +124,6 @@
 		cmp r0, r1
 		blt invalidateDCacheRange_lp
 	bx lr
+
+
+.pool
diff --git a/source/arm9/hardware/exception.s b/source/arm9/hardware/exception.s
index 37215b7..84cde51 100644
--- a/source/arm9/hardware/exception.s
+++ b/source/arm9/hardware/exception.s
@@ -92,3 +92,6 @@
 	msr spsr_fsxc, r0
 irqHandler_skip_processing:
 	ldmfd sp!, {r0-r3, r12, pc}^
+
+
+.pool
diff --git a/source/arm9/start.s b/source/arm9/start.s
index c12ee07..c13c529 100644
--- a/source/arm9/start.s
+++ b/source/arm9/start.s
@@ -114,20 +114,19 @@
 		@ Wait for interrupt
 		mcr p15, 0, r0, c7, c0, 4
 		b _start_lp
-.pool
 
 
 #define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF))
 
 setupExceptionVectors:
-	adr r0, vectorStubs
+	adr r0, _vectorStubs
 	mov r1, #A9_VECTORS_START
 	ldmia r0!, {r2-r9}
 	stmia r1!, {r2-r9}
 	ldm r0, {r2-r5}
 	stm r1, {r2-r5}
 	bx lr
-vectorStubs:
+_vectorStubs:
 	ldr pc, irqHandlerPtr
 	irqHandlerPtr:                  .word irqHandler
 	ldr pc, fiqHandlerPtr
@@ -152,7 +151,6 @@
 	orr r0, r0, #0x50000        @ Enable DTCM and ITCM
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register
 	bx lr
-.pool
 
 
 @ void clearMem(u32 *adr, u32 size)
@@ -313,7 +311,6 @@
 	orr r0, r0, r1              @ Enable MPU, D-Cache and I-Cache
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register
 	bx lr
-.pool
 
 
 @ Needed by libc
@@ -345,4 +342,6 @@
 	mcr p15, 0, r2, c7, c6, 0   @ Invalidate D-Cache
 	mcr p15, 0, r2, c7, c10, 4  @ Drain write buffer
 	bx r3
+
+
 .pool