diff --git a/include/arm9/interrupt.h b/include/arm9/interrupt.h
index c9fa3be..0f6615b 100644
--- a/include/arm9/interrupt.h
+++ b/include/arm9/interrupt.h
@@ -6,7 +6,7 @@
 
 typedef enum
 {
-	INTERRUPT_DMAC_1_0      = (1u<<0), // DMAC = NDMA
+	INTERRUPT_DMAC_1_0      = (1u<<0), // DMAC_1 = NDMA
 	INTERRUPT_DMAC_1_1      = (1u<<1),
 	INTERRUPT_DMAC_1_2      = (1u<<2),
 	INTERRUPT_DMAC_1_3      = (1u<<3),
diff --git a/include/io.h b/include/io.h
index 89d13bc..da617b6 100644
--- a/include/io.h
+++ b/include/io.h
@@ -145,8 +145,8 @@
 #define REG_AESBLKCNT            *((vu32*)(AES_REGS_BASE + 0x004))
 #define REG_AESBLKCNTH1          *((vu16*)(AES_REGS_BASE + 0x004))
 #define REG_AESBLKCNTH2          *((vu16*)(AES_REGS_BASE + 0x006))
-#define REG_AESWRFIFO            *((vu32*)(AES_REGS_BASE + 0x008))
-#define REG_AESRDFIFO            *((vu32*)(AES_REGS_BASE + 0x00C))
+#define REG_AESWRFIFO             ((vu32*)(AES_REGS_BASE + 0x008))
+#define REG_AESRDFIFO             ((vu32*)(AES_REGS_BASE + 0x00C))
 #define REG_AESKEYSEL            *((vu8* )(AES_REGS_BASE + 0x010))
 #define REG_AESKEYCNT            *((vu8* )(AES_REGS_BASE + 0x011))
 #define REG_AESCTR                ((vu32*)(AES_REGS_BASE + 0x020))
diff --git a/source/arm9/crypto.c b/source/arm9/crypto.c
index 24cce5d..7b627ec 100644
--- a/source/arm9/crypto.c
+++ b/source/arm9/crypto.c
@@ -132,20 +132,9 @@
 	else ctrIvNonceSize = 3;
 
 	REG_NDMA0_SRC_ADDR = (u32)in;
-	REG_NDMA0_DST_ADDR = (u32)&REG_AESWRFIFO;
-	REG_NDMA0_WRITE_CNT = 4;
-	REG_NDMA0_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
-	REG_NDMA0_CNT = NDMA_ENABLE | NDMA_REPEATING_MODE | NDMA_BLK_TRANS_WORD_COUNT(2) | NDMA_STARTUP_AES_IN |
-					NDMA_SRC_UPDATE_INC | NDMA_DST_UPDATE_FIXED;
-
-	REG_NDMA1_SRC_ADDR = (u32)&REG_AESRDFIFO;
 	REG_NDMA1_DST_ADDR = (u32)out;
-	REG_NDMA1_WRITE_CNT = 4;
-	REG_NDMA1_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
-	REG_NDMA1_CNT = NDMA_ENABLE | NDMA_REPEATING_MODE | NDMA_BLK_TRANS_WORD_COUNT(2) | NDMA_STARTUP_AES_OUT |
-					NDMA_SRC_UPDATE_FIXED | NDMA_DST_UPDATE_INC;
-
-	REG_IRQ_IE |= (u32)INTERRUPT_AES;
+	REG_NDMA0_CNT |= NDMA_ENABLE;
+	REG_NDMA1_CNT |= NDMA_ENABLE;
 
 	u32 offset = 0;
 	while(offset < size)
@@ -172,8 +161,9 @@
 		}
 	}
 
-	REG_NDMA0_CNT = REG_NDMA1_CNT = 0;
-	REG_IRQ_IE &= ~((u32)INTERRUPT_AES);
+	REG_NDMA0_CNT &= ~NDMA_ENABLE;
+	REG_NDMA1_CNT &= ~NDMA_ENABLE;
+
 	invalidateDCacheRange(out, size);
 }
 
diff --git a/source/arm9/ndma.c b/source/arm9/ndma.c
index 36a460b..d72156a 100644
--- a/source/arm9/ndma.c
+++ b/source/arm9/ndma.c
@@ -11,8 +11,6 @@
 
 void NDMA_copy(u32 *dest, const u32 *source, u32 num)
 {
-	REG_IRQ_IE |= (u32)INTERRUPT_DMAC_1_7;
-
 	REG_NDMA7_SRC_ADDR = (u32)source;
 	REG_NDMA7_DST_ADDR = (u32)dest;
 	REG_NDMA7_WRITE_CNT = num;
@@ -23,14 +21,11 @@
 	{
 		__asm__("mcr p15, 0, %[in], c7, c0, 4\n" : : [in] "r" (0));
 	}
-	REG_IRQ_IE &= ~((u32)INTERRUPT_DMAC_1_7);
 	REG_IRQ_IF = (u32)INTERRUPT_DMAC_1_7;
 }
 
 void NDMA_fill(u32 *dest, u32 value, u32 num)
 {
-	REG_IRQ_IE |= (u32)INTERRUPT_DMAC_1_7;
-
 	REG_NDMA7_DST_ADDR = (u32)dest;
 	REG_NDMA7_WRITE_CNT = num;
 	REG_NDMA7_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
@@ -41,6 +36,5 @@
 	{
 		__asm__("mcr p15, 0, %[in], c7, c0, 4\n" : : [in] "r" (0));
 	}
-	REG_IRQ_IE &= ~((u32)INTERRUPT_DMAC_1_7);
 	REG_IRQ_IF = (u32)INTERRUPT_DMAC_1_7;
 }
diff --git a/source/arm9/pxi.c b/source/arm9/pxi.c
index e970014..75bab8b 100644
--- a/source/arm9/pxi.c
+++ b/source/arm9/pxi.c
@@ -6,7 +6,6 @@
 
 void PXI_init(void)
 {
-	REG_IRQ_IE |= INTERRUPT_PXI_SYNC;
 	REG_PXI_SYNC9 = PXI_INTERRUPT_ENABLE;
 	REG_PXI_CNT9 = PXI_FLUSH_SEND_FIFO | PXI_ENABLE_SEND_RECV_FIFO;
 }
diff --git a/source/arm9/start.s b/source/arm9/start.s
index 2faa394..b2a85ea 100644
--- a/source/arm9/start.s
+++ b/source/arm9/start.s
@@ -18,6 +18,7 @@
 .extern initSystem
 .extern finiSystem
 .extern __libc_init_array
+.extern initHardware
 .extern main
 .extern firm_launch
 .extern __bss_start__
@@ -61,6 +62,9 @@
 	str r0, [r1]
 
 	blx __libc_init_array       @ Initialize ctors and dtors
+	blx initHardware
+	mov r0, #0
+	mov r1, #0
 	blx main
 	cmp r0, #0
 	bne .
diff --git a/source/arm9/system.s b/source/arm9/system.s
index a81d765..a73eb02 100644
--- a/source/arm9/system.s
+++ b/source/arm9/system.s
@@ -62,8 +62,7 @@
 	ldr r0, =(IO_MEM_ARM9_ONLY + 0x1000) @ IRQ regs
 	stmia r0, {r3, r12}                  @ Disable and aknowledge all interrupts
 
-	str r3, [r2]                         @ REG_NDMA_GLOBAL_CNT
-	add r2, r2, #0x1C                    @ REG_NDMA0_CNT
+	str r3, [r2], #0x1C                  @ REG_NDMA_GLOBAL_CNT
 	mov r12, #8
 	loop_disable:
 		str r3, [r2], #0x1C              @ REG_NDMA_CNT(n) = 0
diff --git a/source/arm9/systemInit.c b/source/arm9/systemInit.c
new file mode 100644
index 0000000..1ffb139
--- /dev/null
+++ b/source/arm9/systemInit.c
@@ -0,0 +1,30 @@
+#include "types.h"
+#include "arm9/ndma.h"
+#include "arm9/interrupt.h"
+#include "io.h"
+
+
+
+void initHardware(void)
+{
+	// Enable all interrupts but these
+	REG_IRQ_IE = ~(u32)(INTERRUPT_SDIO_1 | INTERRUPT_SDIO_1_ASYNC | INTERRUPT_SDIO_3 |
+					INTERRUPT_SDIO_3_ASYNC | INTERRUPT_DEBUG_RECV | INTERRUPT_DEBUG_SEND |
+					INTERRUPT_CTR_CARD_2 | INTERRUPT_CGC | INTERRUPT_CGC_DET |
+					INTERRUPT_DMAC_2 | INTERRUPT_DMAC_2_ABORT);
+
+	// Reserve DMA channel 0 and 1 for AES
+	REG_NDMA0_SRC_ADDR = 0;
+	REG_NDMA0_DST_ADDR = (u32)REG_AESWRFIFO;
+	REG_NDMA0_WRITE_CNT = 4;
+	REG_NDMA0_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
+	REG_NDMA0_CNT = NDMA_REPEATING_MODE | NDMA_BLK_TRANS_WORD_COUNT(2) | NDMA_STARTUP_AES_IN |
+					NDMA_SRC_UPDATE_INC | NDMA_DST_UPDATE_FIXED;
+
+	REG_NDMA1_SRC_ADDR = (u32)REG_AESRDFIFO;
+	REG_NDMA1_DST_ADDR = 0;
+	REG_NDMA1_WRITE_CNT = 4;
+	REG_NDMA1_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
+	REG_NDMA1_CNT = NDMA_REPEATING_MODE | NDMA_BLK_TRANS_WORD_COUNT(2) | NDMA_STARTUP_AES_OUT |
+					NDMA_SRC_UPDATE_FIXED | NDMA_DST_UPDATE_INC;
+}
diff --git a/source/arm9/timer.c b/source/arm9/timer.c
index e021fc4..1167327 100644
--- a/source/arm9/timer.c
+++ b/source/arm9/timer.c
@@ -7,17 +7,13 @@
 void startTimer(Timer timer, TimerPrescaler prescaler, u16 ticks, bool enableIrq)
 {
 	REG_TIMER_VAL(timer) = ticks;
-
-	if(enableIrq) REG_IRQ_IE |= ((u32)INTERRUPT_TIMER_0<<timer);
-
 	REG_TIMER_CNT(timer) = TIMER_ENABLE | ((u32)enableIrq<<6) | prescaler;
 }
 
 void stopTimer(Timer timer)
 {
-	REG_IRQ_IE &= ~((u32)INTERRUPT_TIMER_0<<timer);
-	REG_IRQ_IF = ((u32)INTERRUPT_TIMER_0<<timer);
 	REG_TIMER_CNT(timer) = 0;
+	REG_IRQ_IF = ((u32)INTERRUPT_TIMER_0<<timer);
 }
 
 void timerSleep(u32 ms)
@@ -27,8 +23,6 @@
 	REG_TIMER2_VAL = (u16)tmp;
 	REG_TIMER3_VAL = (u16)(tmp>>16);
 
-	REG_IRQ_IE |= (u32)INTERRUPT_TIMER_3;
-
 	REG_TIMER3_CNT = TIMER_ENABLE | TIMER_INTERRUPT_ENABLE | TIMER_COUNT_UP;
 	REG_TIMER2_CNT = TIMER_ENABLE | TIMER_PRESCALER_1024;
 
@@ -36,9 +30,8 @@
 	//{
 		__asm__("mcr p15, 0, %[in], c7, c0, 4\n" : : [in] "r" (0)); // Wait for interrupt
 	//}
-	REG_IRQ_IF = (u32)INTERRUPT_TIMER_3;
-	REG_IRQ_IE &= ~((u32)INTERRUPT_TIMER_3);
 
 	REG_TIMER2_CNT = REG_TIMER3_CNT = 0;
+	REG_IRQ_IF = (u32)INTERRUPT_TIMER_3;
 }