diff --git a/source/arm11/start.s b/source/arm11/start.s index 38d6065..d62f726 100644 --- a/source/arm11/start.s +++ b/source/arm11/start.s @@ -9,13 +9,13 @@ .global _init .global deinitCpu -.type vectors STT_FUNC -.type _start STT_FUNC -.type stubExceptionVectors STT_FUNC -.type clearMem STT_FUNC -.type setupVfp STT_FUNC -.type _init STT_FUNC -.type deinitCpu STT_FUNC +.type vectors %function +.type _start %function +.type stubExceptionVectors %function +.type clearMem %function +.type setupVfp %function +.type _init %function +.type deinitCpu %function .extern __bss_start__ .extern __bss_end__ @@ -66,7 +66,6 @@ mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer mcr p15, 0, r0, c7, c7, 0 @ Invalidate Both Caches. Also flushes the branch target cache mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier - clrex bl stubExceptionVectors @ Stub the vectors in AXIWRAM bootrom vectors jump to @@ -90,6 +89,7 @@ blx setupMmu bl setupVfp + clrex cpsie a blx __libc_init_array @ Initialize ctors and dtors @@ -151,10 +151,10 @@ mov r1, #0xF00000 @ Give full access to cp10/11 in user and privileged mode mcr p15, 0, r1, c1, c0, 2 @ Write Coprocessor Access Control Register mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer - mov r1, #0x40000000 @ Clear exception bits and enable VFP11 - mov r2, #0x3C00000 @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode - fmxr fpexc, r1 @ Write Floating-point exception register - fmxr fpscr, r2 @ Write Floating-Point Status and Control Register + mov r2, #0x40000000 @ Clear exception bits and enable VFP11 + mov r3, #0x3C00000 @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode + fmxr fpexc, r2 @ Write Floating-point exception register + fmxr fpscr, r3 @ Write Floating-Point Status and Control Register bx lr @@ -163,12 +163,16 @@ deinitCpu: - cpsid aif, #0x1F @ System mode mov r3, lr + cpsid aif, #0x1F @ System mode bl stubExceptionVectors bl flushDCache mov r2, #0 + @ Disable VFP11 + fmxr fpscr, r2 @ Write Floating-Point Status and Control Register + fmxr fpexc, r2 @ Write Floating-point exception register + mrc p15, 0, r0, c1, c0, 0 @ Read control register ldr r1, =0xC03805 @ Disable MMU, D-Cache, Program flow prediction, I-Cache, @ high exception vectors, Unaligned data access, @@ -181,13 +185,9 @@ @ and L1 parity checking mcr p15, 0, r0, c1, c0, 1 @ Write Auxiliary Control Register - mcr p15, 0, r0, c7, c5, 4 @ Flush Prefetch Buffer - mcr p15, 0, r0, c7, c7, 0 @ Invalidate Both Caches. Also flushes the branch target cache - mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier - - @ Disable VFP11 - fmxr fpscr, r2 @ Write Floating-Point Status and Control Register - fmxr fpexc, r2 @ Write Floating-point exception register + mcr p15, 0, r2, c7, c5, 4 @ Flush Prefetch Buffer + mcr p15, 0, r2, c7, c7, 0 @ Invalidate Both Caches. Also flushes the branch target cache + mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier clrex bx r3 .pool diff --git a/source/arm9/exception.s b/source/arm9/exception.s index 31884b4..9b7183d 100644 --- a/source/arm9/exception.s +++ b/source/arm9/exception.s @@ -37,7 +37,6 @@ str r2, [sp, #64] @ Save spsr (cpsr) on exception stack mov r4, r0 mov r5, sp - msr cpsr_cxsf, #0xDF @ Disable all interrupts, system mode bl deinitCpu mov r0, r4 mov sp, r5 diff --git a/source/arm9/start.s b/source/arm9/start.s index 8dfbafc..fcbf889 100644 --- a/source/arm9/start.s +++ b/source/arm9/start.s @@ -9,13 +9,13 @@ .global _init .global deinitCpu -.type _start STT_FUNC -.type setupExceptionVectors STT_FUNC -.type setupTcms STT_FUNC -.type clearMem STT_FUNC -.type setupMpu STT_FUNC -.type _init STT_FUNC -.type deinitCpu STT_FUNC +.type _start %function +.type setupExceptionVectors %function +.type setupTcms %function +.type clearMem %function +.type setupMpu %function +.type _init %function +.type deinitCpu %function .extern __bss_start__ .extern __bss_end__ @@ -38,7 +38,7 @@ .word (VERS_MAJOR<<16 | VERS_MINOR) _start: - msr cpsr_cxsf, #0xD3 @ Disable all interrupts, SVC mode + msr cpsr_fsxc, #0xD3 @ Disable all interrupts, SVC mode @ Control register: @ [19] ITCM load mode : disabled @@ -61,19 +61,18 @@ mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer bl setupExceptionVectors @ Setup the vectors in ARM9 mem bootrom vectors jump to + bl setupTcms @ Setup and enable DTCM and ITCM mov sp, #0 @ SVC mode sp (Unused, aborts) - msr cpsr_cxsf, #0xD7 @ Abort mode + msr cpsr_fsxc, #0xD7 @ Abort mode mov sp, #A9_EXC_STACK_END - msr cpsr_cxsf, #0xDB @ Undefined mode + msr cpsr_fsxc, #0xDB @ Undefined mode mov sp, #A9_EXC_STACK_END - msr cpsr_cxsf, #0xD2 @ IRQ mode + msr cpsr_fsxc, #0xD2 @ IRQ mode ldr sp, =A9_IRQ_STACK_END - msr cpsr_cxsf, #0xDF @ System mode + msr cpsr_fsxc, #0xDF @ System mode ldr sp, =A9_STACK_END - bl setupTcms @ Setup and enable DTCM and ITCM - @ Clear bss section ldr r0, =__bss_start__ ldr r1, =__bss_end__ @@ -111,8 +110,8 @@ mov r1, #A9_VECTORS_START ldmia r0!, {r2-r9} stmia r1!, {r2-r9} - ldmia r0, {r2-r5} - stmia r1, {r2-r5} + ldm r0, {r2-r5} + stm r1, {r2-r5} bx lr vectorStubs: ldr pc, irqHandlerPtr @@ -127,14 +126,13 @@ prefetchAbortHandlerPtr: .word prefetchAbortHandler ldr pc, dataAbortHandlerPtr dataAbortHandlerPtr: .word dataAbortHandler -.pool setupTcms: ldr r0, =(DTCM_BASE | 0x0A) @ Base = 0xFFF00000, size = 16 KB + mov r1, #(ITCM_BASE | 0x24) @ Base = 0x00000000, size = 512 KB (32 KB mirrored) mcr p15, 0, r0, c9, c1, 0 @ Write DTCM region reg - mov r0, #(ITCM_BASE | 0x24) @ Base = 0x00000000, size = 512 KB (32 KB mirrored) - mcr p15, 0, r0, c9, c1, 1 @ Write ITCM region reg + mcr p15, 0, r1, c9, c1, 1 @ Write ITCM region reg mrc p15, 0, r0, c1, c0, 0 @ Read control register orr r0, r0, #0x50000 @ Enable DTCM and ITCM @@ -208,27 +206,27 @@ @ Region 0: ITCM kernel mirror 32 KB @ Region 1: ARM9 internal mem 1 MB @ Region 2: IO region 2 MB covers only ARM9 accessible regs - @ Region 3: VRAM 8MB + @ Region 3: VRAM 8 MB @ Region 4: DTCM 16 KB - @ Region 5: - (reserved) + @ Region 5: Exception vectors + ARM9 bootrom 32 KB @ Region 6: - (reserved) - @ Region 7: Exception vectors + ARM9 bootrom 32 KB + @ Region 7: - (reserved) ldr r0, =MAKE_REGION(ITCM_KERNEL_MIRROR, REGION_32KB) mcr p15, 0, r0, c6, c0, 0 - ldr r0, =MAKE_REGION(A9_RAM_BASE, REGION_1MB) - mcr p15, 0, r0, c6, c1, 0 - ldr r0, =MAKE_REGION(IO_MEM_ARM9_ONLY, REGION_2MB) - mcr p15, 0, r0, c6, c2, 0 - ldr r0, =MAKE_REGION(VRAM_BASE, REGION_8MB) - mcr p15, 0, r0, c6, c3, 0 + ldr r1, =MAKE_REGION(A9_RAM_BASE, REGION_1MB) + mcr p15, 0, r1, c6, c1, 0 + ldr r2, =MAKE_REGION(IO_MEM_ARM9_ONLY, REGION_2MB) + mcr p15, 0, r2, c6, c2, 0 + ldr r3, =MAKE_REGION(VRAM_BASE, REGION_8MB) + mcr p15, 0, r3, c6, c3, 0 ldr r0, =MAKE_REGION(DTCM_BASE, REGION_16KB) mcr p15, 0, r0, c6, c4, 0 - mov r0, #0 - mcr p15, 0, r0, c6, c5, 0 - //mov r0, #0 - mcr p15, 0, r0, c6, c6, 0 - ldr r0, =MAKE_REGION(BOOT9_BASE, REGION_32KB) - mcr p15, 0, r0, c6, c7, 0 + ldr r1, =MAKE_REGION(BOOT9_BASE, REGION_32KB) + mcr p15, 0, r1, c6, c5, 0 + mov r2, #0 + mcr p15, 0, r2, c6, c6, 0 + @mov r3, #0 + mcr p15, 0, r2, c6, c7, 0 @ Data access permissions: @ Region 0: User = --, Privileged = RW @@ -236,14 +234,14 @@ @ Region 2: User = --, Privileged = RW @ Region 3: User = --, Privileged = RW @ Region 4: User = --, Privileged = RW - @ Region 5: User = --, Privileged = -- + @ Region 5: User = --, Privileged = RO @ Region 6: User = --, Privileged = -- - @ Region 7: User = --, Privileged = RO + @ Region 7: User = --, Privileged = -- ldr r0, =MAKE_PERMISSIONS(PER_PRIV_RW_USR_NO_ACC, PER_PRIV_RW_USR_NO_ACC, PER_PRIV_RW_USR_NO_ACC, PER_PRIV_RW_USR_NO_ACC, - PER_PRIV_RW_USR_NO_ACC, PER_NO_ACC, - PER_NO_ACC , PER_PRIV_RO_USR_NO_ACC) - mcr p15, 0, r0, c5, c0, 2 @ Data access permissions + PER_PRIV_RW_USR_NO_ACC, PER_PRIV_RO_USR_NO_ACC, + PER_NO_ACC , PER_NO_ACC) + mcr p15, 0, r0, c5, c0, 2 @ Write data access permissions @ Instruction access permissions: @ Region 0: User = --, Privileged = RO @@ -251,14 +249,14 @@ @ Region 2: User = --, Privileged = -- @ Region 3: User = --, Privileged = -- @ Region 4: User = --, Privileged = -- - @ Region 5: User = --, Privileged = -- + @ Region 5: User = --, Privileged = RO @ Region 6: User = --, Privileged = -- - @ Region 7: User = --, Privileged = RO - ldr r0, =MAKE_PERMISSIONS(PER_PRIV_RO_USR_NO_ACC, PER_PRIV_RO_USR_NO_ACC, + @ Region 7: User = --, Privileged = -- + ldr r1, =MAKE_PERMISSIONS(PER_PRIV_RO_USR_NO_ACC, PER_PRIV_RO_USR_NO_ACC, PER_NO_ACC, PER_NO_ACC, - PER_NO_ACC, PER_NO_ACC, - PER_NO_ACC, PER_PRIV_RO_USR_NO_ACC) - mcr p15, 0, r0, c5, c0, 3 @ Instruction access permissions + PER_NO_ACC, PER_PRIV_RO_USR_NO_ACC, + PER_NO_ACC, PER_NO_ACC) + mcr p15, 0, r1, c5, c0, 3 @ Write instruction access permissions @ Data cachable bits: @ Region 0 = no @@ -266,10 +264,10 @@ @ Region 2 = no <-- Never cache IO regs @ Region 3 = yes @ Region 4 = no - @ Region 5 = no + @ Region 5 = yes @ Region 6 = no - @ Region 7 = yes - mov r0, #0b10001010 + @ Region 7 = no + mov r0, #0b00101010 mcr p15, 0, r0, c2, c0, 0 @ Data cachable bits @ Instruction cachable bits: @@ -278,11 +276,11 @@ @ Region 2 = no @ Region 3 = no @ Region 4 = no - @ Region 5 = no + @ Region 5 = yes @ Region 6 = no - @ Region 7 = yes - mov r0, #0b10000010 - mcr p15, 0, r0, c2, c0, 1 @ Instruction cachable bits + @ Region 7 = no + mov r1, #0b00100010 + mcr p15, 0, r1, c2, c0, 1 @ Instruction cachable bits @ Write bufferable bits: @ Region 0 = no @@ -290,11 +288,11 @@ @ Region 2 = no <-- Never buffer IO regs @ Region 3 = yes @ Region 4 = no - @ Region 5 = no + @ Region 5 = yes @ Region 6 = no - @ Region 7 = yes - mov r0, #0b10001010 - mcr p15, 0, r0, c3, c0, 0 @ Write bufferable bits + @ Region 7 = no + mov r2, #0b00101010 + mcr p15, 0, r2, c3, c0, 0 @ Write bufferable bits mrc p15, 0, r0, c1, c0, 0 @ Read control register ldr r1, =0x1005 @ MPU, D-Cache and I-Cache bitmask @@ -310,8 +308,8 @@ deinitCpu: - msr cpsr_cxsf, #0xDF @ System mode mov r3, lr + msr cpsr_fsxc, #0xDF @ System mode @ Stub vectors to endless loops mov r0, #A9_RAM_BASE