diff --git a/include/arm9/ndma.h b/include/arm9/ndma.h
index 890ab76..28553d9 100644
--- a/include/arm9/ndma.h
+++ b/include/arm9/ndma.h
@@ -15,83 +15,83 @@
 
 #define REG_NDMA0_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x04))
 #define REG_NDMA0_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x08))
-#define REG_NDMA0_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x0C))
-#define REG_NDMA0_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x10))
-#define REG_NDMA0_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x14))
+#define REG_NDMA0_TOTAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0x0C)) // Total repeat length in words
+#define REG_NDMA0_LOG_BLK_CNT    *((vu32*)(NDMA_REGS_BASE + 0x10)) // Logical block size in words
+#define REG_NDMA0_INT_CNT        *((vu32*)(NDMA_REGS_BASE + 0x14)) // Timing/interval settings
 #define REG_NDMA0_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x18))
 #define REG_NDMA0_CNT            *((vu32*)(NDMA_REGS_BASE + 0x1C))
 
 #define REG_NDMA1_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x20))
 #define REG_NDMA1_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x24))
-#define REG_NDMA1_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x28))
-#define REG_NDMA1_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x2C))
-#define REG_NDMA1_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x30))
+#define REG_NDMA1_TOTAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0x28))
+#define REG_NDMA1_LOG_BLK_CNT    *((vu32*)(NDMA_REGS_BASE + 0x2C))
+#define REG_NDMA1_INT_CNT        *((vu32*)(NDMA_REGS_BASE + 0x30))
 #define REG_NDMA1_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x34))
 #define REG_NDMA1_CNT            *((vu32*)(NDMA_REGS_BASE + 0x38))
 
 #define REG_NDMA2_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x3C))
 #define REG_NDMA2_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x40))
-#define REG_NDMA2_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x44))
-#define REG_NDMA2_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x48))
-#define REG_NDMA2_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x4C))
+#define REG_NDMA2_TOTAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0x44))
+#define REG_NDMA2_LOG_BLK_CNT    *((vu32*)(NDMA_REGS_BASE + 0x48))
+#define REG_NDMA2_INT_CNT        *((vu32*)(NDMA_REGS_BASE + 0x4C))
 #define REG_NDMA2_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x50))
 #define REG_NDMA2_CNT            *((vu32*)(NDMA_REGS_BASE + 0x54))
 
 #define REG_NDMA3_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x58))
 #define REG_NDMA3_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x5C))
-#define REG_NDMA3_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x60))
-#define REG_NDMA3_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x64))
-#define REG_NDMA3_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x68))
+#define REG_NDMA3_TOTAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0x60))
+#define REG_NDMA3_LOG_BLK_CNT    *((vu32*)(NDMA_REGS_BASE + 0x64))
+#define REG_NDMA3_INT_CNT        *((vu32*)(NDMA_REGS_BASE + 0x68))
 #define REG_NDMA3_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x6C))
 #define REG_NDMA3_CNT            *((vu32*)(NDMA_REGS_BASE + 0x70))
 
 #define REG_NDMA4_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x74))
 #define REG_NDMA4_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x78))
-#define REG_NDMA4_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x7C))
-#define REG_NDMA4_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x80))
-#define REG_NDMA4_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x84))
+#define REG_NDMA4_TOTAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0x7C))
+#define REG_NDMA4_LOG_BLK_CNT    *((vu32*)(NDMA_REGS_BASE + 0x80))
+#define REG_NDMA4_INT_CNT        *((vu32*)(NDMA_REGS_BASE + 0x84))
 #define REG_NDMA4_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x88))
 #define REG_NDMA4_CNT            *((vu32*)(NDMA_REGS_BASE + 0x8C))
 
 #define REG_NDMA5_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x90))
 #define REG_NDMA5_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x94))
-#define REG_NDMA5_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x98))
-#define REG_NDMA5_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x9C))
-#define REG_NDMA5_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xA0))
+#define REG_NDMA5_TOTAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0x98))
+#define REG_NDMA5_LOG_BLK_CNT    *((vu32*)(NDMA_REGS_BASE + 0x9C))
+#define REG_NDMA5_INT_CNT        *((vu32*)(NDMA_REGS_BASE + 0xA0))
 #define REG_NDMA5_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xA4))
 #define REG_NDMA5_CNT            *((vu32*)(NDMA_REGS_BASE + 0xA8))
 
 #define REG_NDMA6_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xAC))
 #define REG_NDMA6_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xB0))
-#define REG_NDMA6_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0xB4))
-#define REG_NDMA6_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0xB8))
-#define REG_NDMA6_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xBC))
+#define REG_NDMA6_TOTAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0xB4))
+#define REG_NDMA6_LOG_BLK_CNT    *((vu32*)(NDMA_REGS_BASE + 0xB8))
+#define REG_NDMA6_INT_CNT        *((vu32*)(NDMA_REGS_BASE + 0xBC))
 #define REG_NDMA6_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xC0))
 #define REG_NDMA6_CNT            *((vu32*)(NDMA_REGS_BASE + 0xC4))
 
 #define REG_NDMA7_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xC8))
 #define REG_NDMA7_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xCC))
-#define REG_NDMA7_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0xD0))
-#define REG_NDMA7_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0xD4))
-#define REG_NDMA7_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xD8))
+#define REG_NDMA7_TOTAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0xD0))
+#define REG_NDMA7_LOG_BLK_CNT    *((vu32*)(NDMA_REGS_BASE + 0xD4))
+#define REG_NDMA7_INT_CNT        *((vu32*)(NDMA_REGS_BASE + 0xD8))
 #define REG_NDMA7_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xDC))
 #define REG_NDMA7_CNT            *((vu32*)(NDMA_REGS_BASE + 0xE0))
 
 #define REG_NDMA_SRC_ADDR(n)     *((vu32*)(NDMA_REGS_BASE + 0x04 + (n * 28)))
 #define REG_NDMA_DST_ADDR(n)     *((vu32*)(NDMA_REGS_BASE + 0x08 + (n * 28)))
-#define REG_NDMA_TRANSFER_CNT(n) *((vu32*)(NDMA_REGS_BASE + 0x0C + (n * 28)))
-#define REG_NDMA_WRITE_CNT(n)    *((vu32*)(NDMA_REGS_BASE + 0x10 + (n * 28)))
-#define REG_NDMA_BLOCK_CNT(n)    *((vu32*)(NDMA_REGS_BASE + 0x14 + (n * 28)))
+#define REG_NDMA_TOTAL_CNT(n)    *((vu32*)(NDMA_REGS_BASE + 0x0C + (n * 28)))
+#define REG_NDMA_LOG_BLK_CNT(n)  *((vu32*)(NDMA_REGS_BASE + 0x10 + (n * 28)))
+#define REG_NDMA_INT_CNT(n)      *((vu32*)(NDMA_REGS_BASE + 0x14 + (n * 28)))
 #define REG_NDMA_FILL_DATA(n)    *((vu32*)(NDMA_REGS_BASE + 0x18 + (n * 28)))
 #define REG_NDMA_CNT(n)          *((vu32*)(NDMA_REGS_BASE + 0x1C + (n * 28)))
 
 
 // REG_NDMA_GLOBAL_CNT
-#define NDMA_ROUND_ROBIN(n)    (1u<<31 | ((u32)log2(n) + 1)<<16 | 1u) // n = number of CPU cycles
+#define NDMA_ROUND_ROBIN(n)    ((u32)log2(n) | (1u<<31) | 1u) // n = number of CPU cycles
 #define NDMA_HIGHEST_PRIO      (1u)
 
-// REG_NDMA_BLOCK_CNT
-#define NDMA_BLOCK_SYS_FREQ    (0u)
+// REG_NDMA_INT_CNT
+#define NDMA_INT_SYS_FREQ      (0u)
 
 // REG_NDMA_CNT
 #define NDMA_DST_UPDATE_INC    (0u)
@@ -103,7 +103,6 @@
 #define NDMA_SRC_UPDATE_FIXED  (2u<<13)
 #define NDMA_SRC_UPDATE_FILL   (3u<<13)
 #define NDMA_SRC_ADDR_RELOAD   (1u<<15)
-#define NDMA_STARTUP_MODE(n)   (n<<24)
 // The block length is 2^n words (Example: 2^15 = 32768 words = 0x20000 bytes)
 #define NDMA_BURST_SIZE(n)     ((u32)log2(n)<<16)
 #define NDMA_REPEATING_MODE    (1u<<29)
@@ -113,22 +112,22 @@
 
  enum
  {
- 	NDMA_STARTUP_UNK_0     = (0<<24),
- 	NDMA_STARTUP_UNK_1     = (1<<24),
- 	NDMA_STARTUP_UNK_2     = (2<<24),
- 	NDMA_STARTUP_UNK_3     = (3<<24),
- 	NDMA_STARTUP_UNK_4     = (4<<24),
- 	NDMA_STARTUP_UNK_5     = (5<<24),
+ 	NDMA_STARTUP_TIMER0    = (0<<24), // Unconfirmed
+ 	NDMA_STARTUP_TIMER1    = (1<<24), // Unconfirmed
+ 	NDMA_STARTUP_TIMER2    = (2<<24), // Unconfirmed
+ 	NDMA_STARTUP_TIMER3    = (3<<24), // Unconfirmed
+ 	NDMA_STARTUP_CTRCARD0  = (4<<24),
+ 	NDMA_STARTUP_CTRCARD1  = (5<<24),
  	NDMA_STARTUP_UNK_6     = (6<<24),
- 	NDMA_STARTUP_UNK_7     = (7<<24),
+ 	NDMA_STARTUP_EMMC      = (7<<24),
  	NDMA_STARTUP_AES_IN    = (8<<24),  // AES write fifo
  	NDMA_STARTUP_AES_OUT   = (9<<24),  // AES read fifo
- 	NDMA_STARTUP_UNK_10    = (10<<24),
+ 	NDMA_STARTUP_SHA       = (10<<24),
  	NDMA_STARTUP_UNK_11    = (11<<24),
  	NDMA_STARTUP_UNK_12    = (12<<24),
  	NDMA_STARTUP_UNK_13    = (13<<24),
  	NDMA_STARTUP_UNK_14    = (14<<24),
- 	NDMA_STARTUP_UNK_15    = (15<<24),
+ 	NDMA_STARTUP_AES_SHA   = (15<<24), // Unconfirmed
  	NDMA_STARTUP_IMMEDIATE = (16<<24)
  };
 
@@ -144,7 +143,7 @@
  *
  * @param      dest    Pointer to destination memory. Must be 4 bytes aligned.
  * @param      source  Pointer to source data. Must be 4 bytes aligned.
- * @param[in]  num     The size of the data. Must be a multiple of 4.
+ * @param[in]  size    The size of the data. Must be multiple of 4.
  */
 void NDMA_copyAsync(u32 *dest, const u32 *source, u32 num);
 
@@ -153,24 +152,24 @@
  *
  * @param      dest    Pointer to destination memory. Must be 4 bytes aligned.
  * @param      source  Pointer to source data. Must be 4 bytes aligned.
- * @param[in]  num     The size of the data. Must be a multiple of 4.
+ * @param[in]  size    The size of the data. Must be multiple of 4.
  */
-void NDMA_copy(u32 *dest, const u32 *source, u32 num);
+void NDMA_copy(u32 *dest, const u32 *source, u32 size);
 
 /**
  * @brief      Asynchronous memory fill with the given value using the NDMA engine.
  *
  * @param      dest   Pointer to destination memory. Must be 4 bytes aligned.
  * @param[in]  value  The value each 32-bit word will be set to.
- * @param[in]  num    The size of the memory to fill. Must be a multiple of 4.
+ * @param[in]  size   The size of the memory to fill. Must be multiple of 4.
  */
-void NDMA_fillAsync(u32 *dest, u32 value, u32 num);
+void NDMA_fillAsync(u32 *dest, u32 value, u32 size);
 
 /**
  * @brief      Fills memory with the given value using the NDMA engine.
  *
  * @param      dest   Pointer to destination memory. Must be 4 bytes aligned.
  * @param[in]  value  The value each 32-bit word will be set to.
- * @param[in]  num    The size of the memory to fill. Must be a multiple of 4.
+ * @param[in]  size   The size of the memory to fill. Must be multiple of 4.
  */
-void NDMA_fill(u32 *dest, u32 value, u32 num);
+void NDMA_fill(u32 *dest, u32 value, u32 size);
diff --git a/source/arm9/crypto.c b/source/arm9/crypto.c
index 345b84f..0abf2b2 100644
--- a/source/arm9/crypto.c
+++ b/source/arm9/crypto.c
@@ -55,15 +55,13 @@
 	REG_AESCNT = AES_MAC_SIZE(4) | AES_FLUSH_WRITE_FIFO | AES_FLUSH_READ_FIFO;
 	*((vu8*)0x10000008) |= 0xCu; // ??
 
-	//REG_NDMA0_CNT = 0;
 	REG_NDMA0_DST_ADDR = (u32)REG_AESWRFIFO;
-	REG_NDMA0_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
+	REG_NDMA0_INT_CNT = NDMA_INT_SYS_FREQ;
 	REG_NDMA0_CNT = NDMA_REPEATING_MODE | NDMA_STARTUP_AES_IN |
 	                NDMA_SRC_UPDATE_INC | NDMA_DST_UPDATE_FIXED;
 
-	//REG_NDMA1_CNT = 0;
 	REG_NDMA1_SRC_ADDR = (u32)REG_AESRDFIFO;
-	REG_NDMA1_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
+	REG_NDMA1_INT_CNT = NDMA_INT_SYS_FREQ;
 	REG_NDMA1_CNT = NDMA_REPEATING_MODE | NDMA_STARTUP_AES_OUT |
 	                NDMA_SRC_UPDATE_FIXED | NDMA_DST_UPDATE_INC;
 
@@ -167,11 +165,11 @@
 static void setupNdma(const u32 *restrict in, u32 *restrict out, u32 wordCount, u32 burstSize)
 {
 	REG_NDMA0_SRC_ADDR = (u32)in;
-	REG_NDMA0_WRITE_CNT = wordCount;
+	REG_NDMA0_LOG_BLK_CNT = wordCount;
 	REG_NDMA0_CNT = (REG_NDMA0_CNT & 0xFFF0FFFFu) | NDMA_ENABLE | burstSize;
 
 	REG_NDMA1_DST_ADDR = (u32)out;
-	REG_NDMA1_WRITE_CNT = wordCount;
+	REG_NDMA1_LOG_BLK_CNT = wordCount;
 	REG_NDMA1_CNT = (REG_NDMA1_CNT & 0xFFF0FFFFu) | NDMA_ENABLE | burstSize;
 }
 
diff --git a/source/arm9/firm.c b/source/arm9/firm.c
index cfb647f..98df7e1 100644
--- a/source/arm9/firm.c
+++ b/source/arm9/firm.c
@@ -107,10 +107,10 @@
 		{
 			REG_NDMA_SRC_ADDR(i) = FIRM_LOAD_ADDR + section->offset;
 			REG_NDMA_DST_ADDR(i) = section->address;
-			REG_NDMA_WRITE_CNT(i) = section->size / 4;
-			REG_NDMA_BLOCK_CNT(i) = NDMA_BLOCK_SYS_FREQ;
-			REG_NDMA_CNT(i) = NDMA_DST_UPDATE_INC | NDMA_SRC_UPDATE_INC |
-			                  NDMA_STARTUP_IMMEDIATE | NDMA_ENABLE;
+			REG_NDMA_LOG_BLK_CNT(i) = section->size / 4;
+			REG_NDMA_INT_CNT(i) = NDMA_INT_SYS_FREQ;
+			REG_NDMA_CNT(i) = NDMA_ENABLE | NDMA_BURST_SIZE(128) | NDMA_STARTUP_IMMEDIATE |
+			                  NDMA_SRC_UPDATE_INC | NDMA_DST_UPDATE_INC;
 		}
 		else
 		{
@@ -252,7 +252,7 @@
 	while(PXI_recvWord() != PXI_RPL_OK);
 	
 	//printf("Relocating FIRM launch stub...\n");
-	NDMA_copy((u32*)A9_STUB_ENTRY, (u32*)firmLaunchStub, A9_STUB_SIZE>>2);
+	NDMA_copy((u32*)A9_STUB_ENTRY, (u32*)firmLaunchStub, A9_STUB_SIZE);
 
 	//printf("Starting firm launch...\n");
 	((void (*)(void))A9_STUB_ENTRY)();
diff --git a/source/arm9/interrupt.c b/source/arm9/interrupt.c
index 0928899..d3ccadc 100644
--- a/source/arm9/interrupt.c
+++ b/source/arm9/interrupt.c
@@ -21,12 +21,20 @@
 
 void IRQ_registerHandler(Interrupt num, void (*irqHandler)(void))
 {
+	const u32 oldState = enterCriticalSection();
+
 	irqHandlerTable[num] = irqHandler;
 	REG_IRQ_IE |= 1u<<num;
+
+	leaveCriticalSection(oldState);
 }
 
 void IRQ_unregisterHandler(Interrupt num)
 {
+	const u32 oldState = enterCriticalSection();
+
 	REG_IRQ_IE &= ~(1u<<num);
 	irqHandlerTable[num] = (void (*)(void))NULL;
+
+	leaveCriticalSection(oldState);
 }
diff --git a/source/arm9/ndma.c b/source/arm9/ndma.c
index a4833cb..281aa3b 100644
--- a/source/arm9/ndma.c
+++ b/source/arm9/ndma.c
@@ -12,8 +12,6 @@
 
 void NDMA_init(void)
 {
-	u32 oldState = enterCriticalSection();
-
 	for(u32 i = 0; i < 8; i++)
 	{
 		REG_NDMA_CNT(i) = (REG_NDMA_CNT(i)<<1)>>1;
@@ -22,25 +20,23 @@
 	REG_NDMA_GLOBAL_CNT = NDMA_ROUND_ROBIN(32);
 
 	REG_IRQ_IE |= 1u<<IRQ_DMAC_1_7;
-
-	leaveCriticalSection(oldState);
 }
 
-void NDMA_copyAsync(u32 *dest, const u32 *source, u32 num)
+void NDMA_copyAsync(u32 *dest, const u32 *source, u32 size)
 {
 	assert(((u32)dest >= ITCM_BOOT9_MIRROR + ITCM_SIZE) && (((u32)dest < DTCM_BASE) || ((u32)dest >= DTCM_BASE + DTCM_SIZE)));
 	assert(((u32)source >= ITCM_BOOT9_MIRROR + ITCM_SIZE) && (((u32)source < DTCM_BASE) || ((u32)source >= DTCM_BASE + DTCM_SIZE)));
 
 	REG_NDMA7_SRC_ADDR = (u32)source;
 	REG_NDMA7_DST_ADDR = (u32)dest;
-	REG_NDMA7_WRITE_CNT = num;
-	REG_NDMA7_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
+	REG_NDMA7_LOG_BLK_CNT = size / 4;
+	REG_NDMA7_INT_CNT = NDMA_INT_SYS_FREQ;
 	REG_NDMA7_CNT = NDMA_ENABLE | NDMA_IRQ_ENABLE | NDMA_STARTUP_IMMEDIATE | NDMA_SRC_UPDATE_INC | NDMA_DST_UPDATE_INC;
 }
 
-void NDMA_copy(u32 *dest, const u32 *source, u32 num)
+void NDMA_copy(u32 *dest, const u32 *source, u32 size)
 {
-	NDMA_copyAsync(dest, source, num);
+	NDMA_copyAsync(dest, source, size);
 
 	while(REG_NDMA7_CNT & NDMA_ENABLE)
 	{
@@ -48,20 +44,20 @@
 	}
 }
 
-void NDMA_fillAsync(u32 *dest, u32 value, u32 num)
+void NDMA_fillAsync(u32 *dest, u32 value, u32 size)
 {
 	assert(((u32)dest >= ITCM_BOOT9_MIRROR + ITCM_SIZE) && (((u32)dest < DTCM_BASE) || ((u32)dest >= DTCM_BASE + DTCM_SIZE)));
 
 	REG_NDMA7_DST_ADDR = (u32)dest;
-	REG_NDMA7_WRITE_CNT = num;
-	REG_NDMA7_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
+	REG_NDMA7_LOG_BLK_CNT = size / 4;
+	REG_NDMA7_INT_CNT = NDMA_INT_SYS_FREQ;
 	REG_NDMA7_FILL_DATA = value;
 	REG_NDMA7_CNT = NDMA_ENABLE | NDMA_IRQ_ENABLE | NDMA_STARTUP_IMMEDIATE | NDMA_SRC_UPDATE_FILL | NDMA_DST_UPDATE_INC;
 }
 
-void NDMA_fill(u32 *dest, u32 value, u32 num)
+void NDMA_fill(u32 *dest, u32 value, u32 size)
 {
-	NDMA_fillAsync(dest, value, num);
+	NDMA_fillAsync(dest, value, size);
 
 	while(REG_NDMA7_CNT & NDMA_ENABLE)
 	{
diff --git a/source/arm9/pxi.c b/source/arm9/pxi.c
index 25ed9e0..d4f5833 100644
--- a/source/arm9/pxi.c
+++ b/source/arm9/pxi.c
@@ -6,8 +6,6 @@
 
 void PXI_init(void)
 {
-	u32 oldState = enterCriticalSection();
-
 	REG_PXI_SYNC9 = PXI_IRQ_ENABLE;
 	REG_PXI_CNT9 = PXI_FLUSH_SEND_FIFO | PXI_EMPTY_FULL_ERROR | PXI_ENABLE_SEND_RECV_FIFO;
 
@@ -15,8 +13,6 @@
 	while((REG_PXI_SYNC9 & 0xFFu) != 11u);
 
 	REG_IRQ_IE |= 1u<<IRQ_PXI_SYNC;
-
-	leaveCriticalSection(oldState);
 }
 
 void PXI_sendWord(u32 val)
diff --git a/source/arm9/timer.c b/source/arm9/timer.c
index 0245d5a..8bdec2b 100644
--- a/source/arm9/timer.c
+++ b/source/arm9/timer.c
@@ -28,16 +28,12 @@
 
 void TIMER_init(void)
 {
-	u32 oldState = enterCriticalSection();
-
 	for(u32 i = 0; i < 4; i++)
 	{
 		REG_TIMER_CNT(i) = 0;
 	}
 
 	REG_IRQ_IE |= 1u<<IRQ_TIMER_3;
-
-	leaveCriticalSection(oldState);
 }
 
 void TIMER_start(Timer timer, TimerPrescaler prescaler, u16 ticks, bool enableIrq)