diff --git a/include/util.h b/include/util.h
index 57cf7ed..33893e6 100644
--- a/include/util.h
+++ b/include/util.h
@@ -26,7 +26,7 @@
 
 
 
-void wait(u32 cycles);
+NAKED void wait(u32 cycles);
 
 // case insensitive string compare function
 int strnicmp(const char *str1, const char *str2, u32 len);
diff --git a/source/arm11/hardware/gfx.c b/source/arm11/hardware/gfx.c
index 9d6ea6e..57371c2 100644
--- a/source/arm11/hardware/gfx.c
+++ b/source/arm11/hardware/gfx.c
@@ -30,6 +30,7 @@
 #include "arm11/hardware/interrupt.h"
 #include "arm11/hardware/timer.h"
 #include "arm.h"
+//#include "util.h"
 
 
 #define PDN_REGS_BASE           (IO_MEM_ARM9_ARM11 + 0x40000)
@@ -250,6 +251,8 @@
 {
 	if(REG_PDN_GPU_CNT != 0x1007F) // Check if screens are already initialized
 	{
+		//REG_PDN_GPU_CNT = 0x10000;
+		//wait(134);
 		REG_PDN_GPU_CNT = 0x1007F;
 		*((vu32*)0x10202014) = 0x00000001;
 		*((vu32*)0x1020200C) &= 0xFFFEFFFE;
diff --git a/source/arm11/hardware/mmu.c b/source/arm11/hardware/mmu.c
index 5938972..8bd5cd9 100644
--- a/source/arm11/hardware/mmu.c
+++ b/source/arm11/hardware/mmu.c
@@ -181,7 +181,8 @@
 		            0, true, L1_TO_L2(ATTR_SHARED_DEVICE));
 
 		// VRAM mapping
-		mmuMapSections(VRAM_BASE, VRAM_BASE, 6, true, PERM_PRIV_RW_USR_NA, 0, true, ATTR_NORM_WRITE_TROUGH_NO_ALLOC);
+		mmuMapSections(VRAM_BASE, VRAM_BASE, 6, true, PERM_PRIV_RW_USR_NA, 0,
+		               true, ATTR_NORM_WRITE_TROUGH_NO_ALLOC);
 
 		// AXIWRAM core 0/1 stack mapping
 		mmuMapPages(A11_C0_STACK_START, A11_C0_STACK_START, 4, mmuTables->l2Axiwram,
@@ -222,7 +223,7 @@
 		// Invalidate tag RAMs before enabling SMP as recommended by the MPCore doc.
 		REG_SCU_CNT = 0x1FFE;        // Disable SCU and parity checking. Access to all CPUs interfaces.
 		REG_SCU_INVAL_TAG = 0xFFFF;  // Invalidate SCU tag RAMs of all CPUs.
-		REG_SCU_CNT |= 0x2001u;      // Enable SCU and parity checking.
+		REG_SCU_CNT = 0x1FFEu | 1;   // Enable SCU.
 
 		syncFlag = true;
 		__sev();
@@ -236,9 +237,8 @@
 
 
 	// Enable Return stack, Dynamic branch prediction, Static branch prediction,
-	// Instruction folding, SMP mode: the CPU is taking part in coherency
-	// and L1 parity checking
-	__setAcr(__getAcr() | 0x6F);
+	// Instruction folding and SMP mode: the CPU is taking part in coherency
+	__setAcr(__getAcr() | 0x2F);
 
 	// Enable MMU, D-Cache, Program flow prediction,
 	// I-Cache, high exception vectors, Unaligned data access,
diff --git a/source/arm9/hardware/sdmmc.c b/source/arm9/hardware/sdmmc.c
index 34d937d..c523330 100644
--- a/source/arm9/hardware/sdmmc.c
+++ b/source/arm9/hardware/sdmmc.c
@@ -451,9 +451,11 @@
 
 int SD_Init()
 {
-	// We need to send at least 74 clock pulses.
+	// We need to send at least 74 clock pulses before talking to the card.
 	set_target(&handleSD);
-	wait(0x1980); // ~75-76 clocks
+	// TMIO base clock is half of the CPU clock so 2 CPU cycles = 1 base clock pulse.
+	// cycles = 2 * [TMIO clock divider] * 74
+	wait(2 * 128 * 74);
 
 	sdmmc_send_command(&handleSD,0,0);
 	sdmmc_send_command(&handleSD,0x10408,0x1AA);
diff --git a/source/util.c b/source/util.c
index 5b59c28..a2fe0cd 100644
--- a/source/util.c
+++ b/source/util.c
@@ -23,12 +23,15 @@
 
 
 
-void NAKED wait(u32 cycles)
+NAKED void wait(u32 cycles)
 {
-	__asm__("subs %0, %0, #2\n"
-	        "nop\n"
-	        "bgt wait\n"
-	        "bx lr" : : "r" (cycles) : "cc", "memory");
+#ifdef ARM9
+	__asm__("subs %0, %0, #4\n\t"
+#elif ARM11
+	__asm__("subs %0, %0, #5\n\t"
+#endif
+	        "bcs wait\n\t"
+	        "bx lr" : : "r" (cycles) : "cc");
 }
 
 // case insensitive string compare function