diff --git a/source/arm11/cpu.s b/source/arm11/cpu.s
index 2fedad4..7b1e1b7 100644
--- a/source/arm11/cpu.s
+++ b/source/arm11/cpu.s
@@ -110,8 +110,9 @@
 	bl flushDCache
 	mov r2, #0
 	mrc p15, 0, r0, c1, c0, 0   @ Read control register
-	ldr r1, =0x803805           @ MMU, D-Cache, Program flow prediction, I-Cache,
-                                @ high exception vectors, subpage AP bits disabled
+	ldr r1, =0x803807           @ Enable MMU, Strict data address alignment fault, D-Cache,
+                                @ Program flow prediction, I-Cache, high exception vectors,
+                                @ subpage AP bits disabled
 	bic r0, r0, r1
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register
 	mrc p15, 0, r0, c1, c0, 1   @ Read Auxiliary Control Register