diff --git a/source/arm11/mmu.c b/source/arm11/mmu.c
index ec5ea9c..72bd224 100644
--- a/source/arm11/mmu.c
+++ b/source/arm11/mmu.c
@@ -34,7 +34,7 @@
 
 
 extern void clearMem(u32 *adr, u32 size);
-extern u32 __start__;
+extern u32 __start__[];
 
 /**
  * @brief      Maps up to 4096 1 MB sections of memory.
@@ -119,7 +119,7 @@
 	            L1_TO_L2(MAKE_CUSTOM_NORM_ATTR(POLICY_WRITE_BACK_ALLOC_BUFFERED, POLICY_WRITE_BACK_ALLOC_BUFFERED)));
 
 	// Map boot11 mirror to loader executable start (exception vectors)
-	mmuMapPages(BOOT11_MIRROR2, (u32)&__start__, 1, (u32*)(A11_MMU_TABLES_BASE + 0x4800u), true,
+	mmuMapPages(BOOT11_MIRROR2, (u32)__start__, 1, (u32*)(A11_MMU_TABLES_BASE + 0x4800u), true,
 	            PERM_PRIV_RO_USR_NO_ACC, 1, false,
 	            L1_TO_L2(MAKE_CUSTOM_NORM_ATTR(POLICY_WRITE_BACK_ALLOC_BUFFERED, POLICY_WRITE_BACK_ALLOC_BUFFERED)));
 
@@ -150,4 +150,10 @@
 	                  // I-Cache, high exception vectors, Unaligned data access,
 	                  // subpage AP bits disabled
 	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0" : : "r" (tmp));
+
+	// Invalidate all caches + Data Synchronization Barrier
+	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4\n\t"
+	                     "mcr p15, 0, %0, c7, c5, 0\n\t"
+	                     "mcr p15, 0, %0, c7, c6, 0\n\t"
+	                     "mcr p15, 0, %0, c7, c10, 4" : : "r" (0u));
 }
diff --git a/source/arm11/start.s b/source/arm11/start.s
index fc573ea..c43374b 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -63,9 +63,10 @@
 	mov r0, #0
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
 
-	mcr p15, 0, r0, c7, c5, 4   @ Flush Prefetch Buffer
-	mcr p15, 0, r0, c7, c7, 0   @ Invalidate Both Caches. Also flushes the branch target cache
-	mcr p15, 0, r0, c7, c10, 4  @ Data Synchronization Barrier
+	mcr p15, 0, r0, c7, c5, 4  @ Flush Prefetch Buffer
+	mcr p15, 0, r0, c7, c5, 0  @ Invalidate Entire Instruction Cache. Also flushes the branch target cache
+	mcr p15, 0, r0, c7, c6, 0  @ Invalidate Entire Data Cache
+	mcr p15, 0, r0, c7, c10, 4 @ Data Synchronization Barrier
 
 	bl stubExceptionVectors     @ Stub the vectors in AXIWRAM bootrom vectors jump to
 
@@ -183,9 +184,10 @@
 	                            @ and L1 parity checking
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
 
-	mcr p15, 0, r2, c7, c5, 4   @ Flush Prefetch Buffer
-	mcr p15, 0, r2, c7, c7, 0   @ Invalidate Both Caches. Also flushes the branch target cache
-	mcr p15, 0, r2, c7, c10, 4  @ Data Synchronization Barrier
+	mcr p15, 0, r2, c7, c5, 4  @ Flush Prefetch Buffer
+	mcr p15, 0, r2, c7, c5, 0  @ Invalidate Entire Instruction Cache. Also flushes the branch target cache
+	mcr p15, 0, r2, c7, c6, 0  @ Invalidate Entire Data Cache
+	mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
 
 	@ Disable VFP11
 	fmxr fpscr, r2              @ Write Floating-Point Status and Control Register