diff --git a/source/arm11/hardware.c b/source/arm11/hardware.c
index 078feed..586f56e 100644
--- a/source/arm11/hardware.c
+++ b/source/arm11/hardware.c
@@ -1,4 +1,5 @@
 #include "types.h"
+#include "arm11/start.h"
 #include "arm11/interrupt.h"
 #include "arm11/timer.h"
 #include "pxi.h"
@@ -10,8 +11,18 @@
 {
 	IRQ_init();
 	TIMER_init();
-	PXI_init();
-	hidInit();
+
+	if(!getCpuId())
+	{
+		PXI_init();
+		hidInit();
+	}
+	else
+	{
+		// We don't need core 1 yet so back it goes into boot11.
+		deinitCpu();
+		((void (*)(void))0x0001004C)();
+	}
 }
 
 /*void hardwareDeinit(void)
diff --git a/source/arm11/mmu.c b/source/arm11/mmu.c
index 5d38a15..5b618fc 100644
--- a/source/arm11/mmu.c
+++ b/source/arm11/mmu.c
@@ -1,7 +1,7 @@
 #include "types.h"
 #include "mem_map.h"
 #include "arm11/start.h"
-
+#include "arm11/interrupt.h"
 
 
 #define SCU_REGS_BASE      (MPCORE_PRIV_REG_BASE)
@@ -11,6 +11,7 @@
 #define REG_SCU_INVAL_TAG  *((vu32*)(SCU_REGS_BASE + 0x0C))
 
 
+
 // Mem permissions
 #define PERM_NO_ACC                            (0b000000u)
 #define PERM_PRIV_RW_USR_NO_ACC                (0b000001u)
@@ -99,6 +100,7 @@
 	__asm__ __volatile__("mcr p15, 0, %0, c13, c0, 1" : : "r" (0u));
 
 
+	static volatile bool syncFlag = false;
 	if(!getCpuId())
 	{
 		// Clear L1 and L2 tables
@@ -131,7 +133,16 @@
 		mmuMapPages(BOOT11_MIRROR2, (u32)__start__, 1, (u32*)(A11_MMU_TABLES_BASE + 0x4800u), true,
 		            PERM_PRIV_RO_USR_NO_ACC, 1, false,
 		            L1_TO_L2(MAKE_CUSTOM_NORM_ATTR(POLICY_WRITE_BACK_ALLOC_BUFFERED, POLICY_WRITE_BACK_ALLOC_BUFFERED)));
+
+		// Invalidate tag RAMs before enabling SMP as recommended by the MPCore doc.
+		REG_SCU_CNT = 0x1FFE;        // Disable SCU and parity checking. Access to all CPUs interfaces.
+		REG_SCU_INVAL_TAG = 0xFFFF;  // Invalidate SCU tag RAMs of all CPUs.
+		REG_SCU_CNT |= 0x2001u;      // Enable SCU and parity checking.
+
+		syncFlag = true;
+		signalEvent();
 	}
+	else while(!syncFlag) waitForEvent();
 
 
 	// Invalidate TLB (Unified TLB operation) + Data Synchronization Barrier
@@ -139,13 +150,6 @@
 	                     "mcr p15, 0, %0, c7, c10, 4" : : "r" (0u));
 
 
-	// Invalidate tag RAMs before enabling SMP as recommended by the MPCore doc.
-	// TODO: SMP mode needs to be enabled with all cores running. This is not correct as is.
-	REG_SCU_CNT = 0x1FFE;        // Disable SCU and parity checking. Access to all CPUs interfaces.
-	REG_SCU_INVAL_TAG = 0xFFFF;  // Invalidate SCU tag RAMs of all CPUs.
-	REG_SCU_CNT |= 0x2001u;      // Enable SCU and parity checking.
-
-
 	u32 tmp;
 	// Modify Auxiliary Control Register
 	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r" (tmp) : );
diff --git a/source/arm11/start.s b/source/arm11/start.s
index 048edb8..edb5526 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -76,7 +76,10 @@
 	mcr p15, 0, r0, c7, c7, 0   @ Invalidate Both Caches. Also flushes the branch target cache
 	mcr p15, 0, r0, c7, c10, 4  @ Data Synchronization Barrier
 
-	bl stubExceptionVectors     @ Stub the vectors in AXIWRAM bootrom vectors jump to
+	mrc p15, 0, r4, c0, c0, 5   @ Get CPU ID
+	ands r4, r4, #3
+
+	bleq stubExceptionVectors   @ Stub the vectors in AXIWRAM bootrom vectors jump to
 
 	mov sp, #0                  @ SVC mode sp (unused, aborts)
 	cpsid aif, #23              @ Abort mode
@@ -88,7 +91,11 @@
 	cpsid aif, #18              @ IRQ mode
 	mov sp, #0                  @ IRQ mode stack is not needed
 	cpsid aif, #31              @ System mode
-	ldr sp, =A11_STACK_END
+	adr r2, _sysmode_stacks
+	ldr sp, [r2, r4, lsl #2]
+
+	cmp r4, #0
+	bne _start_skip_bss_init_array
 
 	@ Clear bss section
 	ldr r0, =__bss_start__
@@ -96,20 +103,36 @@
 	sub r1, r1, r0
 	bl clearMem
 
+	blx __libc_init_array       @ Initialize ctors and dtors
+
+	@ Wakeup core 1.
+	ldr r0, =0x1FFFFFDC
+	ldr r1, =(MPCORE_PRIV_REG_BASE + 0x1F00)
+	adr r2, _start
+	str r2, [r0]
+	mov r3, #1<<17
+	orr r3, r3, #1
+	str r3, [r1]
+
+_start_skip_bss_init_array:
 	blx setupMmu
 	bl setupVfp
 	clrex
 	cpsie a
 
-	blx __libc_init_array      @ Initialize ctors and dtors
-
-	mov r0, #0                 @ argc
-	mov r1, #0                 @ argv
+	mov r0, #0                  @ argc
+	mov r1, #0                  @ argv
 	blx main
-	fail_loop:
+	_start_lp:
 		wfi
-		b fail_loop
+		b _start_lp
 .pool
+_sysmode_stacks:
+	.word A11_STACK_END
+	.word (VRAM_BASE + VRAM_SIZE) @ Stack for core 1 for now.
+	                              @ Since we don't use core 1 this should be ok
+	.word 0
+	.word 0
 
 
 #define MAKE_BRANCH(src, dst) (0xEA000000 | (((((dst) - (src)) >> 2) - 2) & 0xFFFFFF))