diff --git a/include/arm11/i2c.h b/include/arm11/i2c.h
index de74121..385a5fd 100644
--- a/include/arm11/i2c.h
+++ b/include/arm11/i2c.h
@@ -1,5 +1,7 @@
 #pragma once
 
+#include "types.h"
+
 
 
 // general i2c routines
@@ -18,12 +20,12 @@
 
 // mcu hid
 u8 i2cmcu_readreg_hid();
-#define MCU_HID_POWER_BUTTON_PRESSED		1
-#define MCU_HID_POWER_BUTTON_LONG_PRESSED	1<<1
-#define MCU_HID_HOME_BUTTON_PRESSED			1<<2
-#define MCU_HID_HOME_BUTTON_RELEASED		1<<3
-#define MCU_HID_SHELL_GOT_CLOSED			1<<5
-#define MCU_HID_SHELL_GOT_OPENED			1<<6
+#define MCU_HID_POWER_BUTTON_PRESSED       (1u)
+#define MCU_HID_POWER_BUTTON_LONG_PRESSED  (1u<<1)
+#define MCU_HID_HOME_BUTTON_PRESSED        (1u<<2)
+#define MCU_HID_HOME_BUTTON_RELEASED       (1u<<3)
+#define MCU_HID_SHELL_GOT_CLOSED           (1u<<5)
+#define MCU_HID_SHELL_GOT_OPENED           (1u<<6)
 
 // device 5/6
 u32 i2c_write_regdata_dev5_dev6(bool dev5, bool dev6, u32 regaddr, u8 data);
diff --git a/include/arm9/crypto.h b/include/arm9/crypto.h
index fc31048..17f261d 100644
--- a/include/arm9/crypto.h
+++ b/include/arm9/crypto.h
@@ -1,15 +1,13 @@
 /*
  *  AES code based on code from Normmatt
  *
- *  2016
+ *  2016 - 2017
  *  profi200
  */
 
 #pragma once
 
 #include "types.h"
-#include "io.h"
-
 
 
 //////////////////////////////////
diff --git a/include/arm9/interrupt.h b/include/arm9/interrupt.h
index 5d8d671..f966948 100644
--- a/include/arm9/interrupt.h
+++ b/include/arm9/interrupt.h
@@ -1,9 +1,12 @@
 #pragma once
 
-#include "io.h"
+#include "mem_map.h"
+#include "types.h"
 
 
-#define waitForIrq()      __asm__ __volatile__("mcr p15, 0, %0, c7, c0, 4" : : "r" (0))
+#define IRQ_REGS_BASE  (IO_MEM_ARM9_ONLY + 0x1000)
+#define REG_IRQ_IE     *((vu32*)(IRQ_REGS_BASE + 0x00))
+#define REG_IRQ_IF     *((vu32*)(IRQ_REGS_BASE + 0x04))
 
 
 typedef enum
@@ -46,6 +49,11 @@
 void IRQ_registerHandler(Interrupt num, void (*irqHandler)(void));
 void IRQ_unregisterHandler(Interrupt num);
 
+static inline void waitForIrq(void)
+{
+	__asm__ __volatile__("mcr p15, 0, %0, c7, c0, 4" : : "r" (0));
+}
+
 inline u32 enterCriticalSection(void)
 {
 	u32 tmp;
diff --git a/include/arm9/ndma.h b/include/arm9/ndma.h
index a0426eb..d3e1d6d 100644
--- a/include/arm9/ndma.h
+++ b/include/arm9/ndma.h
@@ -6,10 +6,85 @@
 #pragma once
 
 #include <tgmath.h>
+#include "mem_map.h"
 #include "types.h"
-#include "io.h"
 
 
+#define NDMA_REGS_BASE           (IO_MEM_ARM9_ONLY + 0x2000)
+#define REG_NDMA_GLOBAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0x00))
+
+#define REG_NDMA0_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x04))
+#define REG_NDMA0_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x08))
+#define REG_NDMA0_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x0C))
+#define REG_NDMA0_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x10))
+#define REG_NDMA0_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x14))
+#define REG_NDMA0_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x18))
+#define REG_NDMA0_CNT            *((vu32*)(NDMA_REGS_BASE + 0x1C))
+
+#define REG_NDMA1_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x20))
+#define REG_NDMA1_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x24))
+#define REG_NDMA1_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x28))
+#define REG_NDMA1_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x2C))
+#define REG_NDMA1_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x30))
+#define REG_NDMA1_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x34))
+#define REG_NDMA1_CNT            *((vu32*)(NDMA_REGS_BASE + 0x38))
+
+#define REG_NDMA2_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x3C))
+#define REG_NDMA2_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x40))
+#define REG_NDMA2_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x44))
+#define REG_NDMA2_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x48))
+#define REG_NDMA2_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x4C))
+#define REG_NDMA2_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x50))
+#define REG_NDMA2_CNT            *((vu32*)(NDMA_REGS_BASE + 0x54))
+
+#define REG_NDMA3_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x58))
+#define REG_NDMA3_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x5C))
+#define REG_NDMA3_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x60))
+#define REG_NDMA3_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x64))
+#define REG_NDMA3_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x68))
+#define REG_NDMA3_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x6C))
+#define REG_NDMA3_CNT            *((vu32*)(NDMA_REGS_BASE + 0x70))
+
+#define REG_NDMA4_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x74))
+#define REG_NDMA4_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x78))
+#define REG_NDMA4_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x7C))
+#define REG_NDMA4_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x80))
+#define REG_NDMA4_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x84))
+#define REG_NDMA4_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x88))
+#define REG_NDMA4_CNT            *((vu32*)(NDMA_REGS_BASE + 0x8C))
+
+#define REG_NDMA5_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x90))
+#define REG_NDMA5_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x94))
+#define REG_NDMA5_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x98))
+#define REG_NDMA5_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x9C))
+#define REG_NDMA5_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xA0))
+#define REG_NDMA5_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xA4))
+#define REG_NDMA5_CNT            *((vu32*)(NDMA_REGS_BASE + 0xA8))
+
+#define REG_NDMA6_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xAC))
+#define REG_NDMA6_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xB0))
+#define REG_NDMA6_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0xB4))
+#define REG_NDMA6_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0xB8))
+#define REG_NDMA6_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xBC))
+#define REG_NDMA6_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xC0))
+#define REG_NDMA6_CNT            *((vu32*)(NDMA_REGS_BASE + 0xC4))
+
+#define REG_NDMA7_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xC8))
+#define REG_NDMA7_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xCC))
+#define REG_NDMA7_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0xD0))
+#define REG_NDMA7_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0xD4))
+#define REG_NDMA7_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xD8))
+#define REG_NDMA7_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xDC))
+#define REG_NDMA7_CNT            *((vu32*)(NDMA_REGS_BASE + 0xE0))
+
+#define REG_NDMA_SRC_ADDR(n)     *((vu32*)(NDMA_REGS_BASE + 0x04 + (n * 28)))
+#define REG_NDMA_DST_ADDR(n)     *((vu32*)(NDMA_REGS_BASE + 0x08 + (n * 28)))
+#define REG_NDMA_TRANSFER_CNT(n) *((vu32*)(NDMA_REGS_BASE + 0x0C + (n * 28)))
+#define REG_NDMA_WRITE_CNT(n)    *((vu32*)(NDMA_REGS_BASE + 0x10 + (n * 28)))
+#define REG_NDMA_BLOCK_CNT(n)    *((vu32*)(NDMA_REGS_BASE + 0x14 + (n * 28)))
+#define REG_NDMA_FILL_DATA(n)    *((vu32*)(NDMA_REGS_BASE + 0x18 + (n * 28)))
+#define REG_NDMA_CNT(n)          *((vu32*)(NDMA_REGS_BASE + 0x1C + (n * 28)))
+
 
 // REG_NDMA_GLOBAL_CNT
 #define NDMA_ROUND_ROBIN(n)    (1u<<31 | ((u32)log2(n) + 1)<<16 | 1u) // n = number of CPU cycles
@@ -38,23 +113,23 @@
 
  enum
  {
- 	NDMA_STARTUP_UNK_0      = (0<<24),
- 	NDMA_STARTUP_UNK_1      = (1<<24),
- 	NDMA_STARTUP_UNK_2      = (2<<24),
- 	NDMA_STARTUP_UNK_3      = (3<<24),
- 	NDMA_STARTUP_UNK_4      = (4<<24),
- 	NDMA_STARTUP_UNK_5      = (5<<24),
- 	NDMA_STARTUP_UNK_6      = (6<<24),
- 	NDMA_STARTUP_UNK_7      = (7<<24),
- 	NDMA_STARTUP_AES_IN     = (8<<24),  // AES write fifo
- 	NDMA_STARTUP_AES_OUT    = (9<<24),  // AES read fifo
- 	NDMA_STARTUP_UNK_10     = (10<<24),
- 	NDMA_STARTUP_UNK_11     = (11<<24),
- 	NDMA_STARTUP_UNK_12     = (12<<24),
- 	NDMA_STARTUP_UNK_13     = (13<<24),
- 	NDMA_STARTUP_UNK_14     = (14<<24),
- 	NDMA_STARTUP_UNK_15     = (15<<24),
- 	NDMA_STARTUP_IMMEDIATE  = (16<<24)
+ 	NDMA_STARTUP_UNK_0     = (0<<24),
+ 	NDMA_STARTUP_UNK_1     = (1<<24),
+ 	NDMA_STARTUP_UNK_2     = (2<<24),
+ 	NDMA_STARTUP_UNK_3     = (3<<24),
+ 	NDMA_STARTUP_UNK_4     = (4<<24),
+ 	NDMA_STARTUP_UNK_5     = (5<<24),
+ 	NDMA_STARTUP_UNK_6     = (6<<24),
+ 	NDMA_STARTUP_UNK_7     = (7<<24),
+ 	NDMA_STARTUP_AES_IN    = (8<<24),  // AES write fifo
+ 	NDMA_STARTUP_AES_OUT   = (9<<24),  // AES read fifo
+ 	NDMA_STARTUP_UNK_10    = (10<<24),
+ 	NDMA_STARTUP_UNK_11    = (11<<24),
+ 	NDMA_STARTUP_UNK_12    = (12<<24),
+ 	NDMA_STARTUP_UNK_13    = (13<<24),
+ 	NDMA_STARTUP_UNK_14    = (14<<24),
+ 	NDMA_STARTUP_UNK_15    = (15<<24),
+ 	NDMA_STARTUP_IMMEDIATE = (16<<24)
  };
 
 
diff --git a/include/arm9/spiflash.h b/include/arm9/spiflash.h
index fe60e09..d6ce35d 100644
--- a/include/arm9/spiflash.h
+++ b/include/arm9/spiflash.h
@@ -1,9 +1,12 @@
-
 #pragma once
 
+#include "types.h"
 
-#define SPIFLASH_CMD_RDSR   0x05
-#define SPIFLASH_CMD_READ   0x03
+
+#define SPIFLASH_CMD_RDSR  (0x05)
+#define SPIFLASH_CMD_READ  (0x03)
+
+
 
 // true if spiflash is installed, false otherwise
 bool spiflash_get_status();
diff --git a/include/arm9/timer.h b/include/arm9/timer.h
index e85bc75..3c3231f 100644
--- a/include/arm9/timer.h
+++ b/include/arm9/timer.h
@@ -1,8 +1,6 @@
 #pragma once
 
 #include "types.h"
-#include "io.h"
-
 
 
 #define TIMER_BASE_FREQ     (67027964.0)
diff --git a/include/gfx.h b/include/gfx.h
index f193909..21aae5c 100644
--- a/include/gfx.h
+++ b/include/gfx.h
@@ -1,18 +1,18 @@
 #pragma once
 
-#include "types.h"
 #include "mem_map.h"
+#include "types.h"
 
 
-#define SCREEN_HEIGHT_TOP	240
-#define SCREEN_WIDTH_TOP	400
-#define SCREEN_HEIGHT_SUB	240
-#define SCREEN_WIDTH_SUB	320
+#define SCREEN_HEIGHT_TOP   (240)
+#define SCREEN_WIDTH_TOP    (400)
+#define SCREEN_HEIGHT_SUB   (240)
+#define SCREEN_WIDTH_SUB    (320)
 
-#define FRAMEBUF_TOP_A_1 (VRAM_BASE)
-#define FRAMEBUF_TOP_A_2 (VRAM_BASE)
-#define FRAMEBUF_SUB_A_1 (VRAM_BASE + (SCREEN_WIDTH_TOP * SCREEN_HEIGHT_TOP * 2))
-#define FRAMEBUF_SUB_A_2 (VRAM_BASE + (SCREEN_WIDTH_TOP * SCREEN_HEIGHT_TOP * 2))
+#define FRAMEBUF_TOP_A_1    (VRAM_BASE)
+#define FRAMEBUF_TOP_A_2    (VRAM_BASE)
+#define FRAMEBUF_SUB_A_1    (VRAM_BASE + (SCREEN_WIDTH_TOP * SCREEN_HEIGHT_TOP * 2))
+#define FRAMEBUF_SUB_A_2    (VRAM_BASE + (SCREEN_WIDTH_TOP * SCREEN_HEIGHT_TOP * 2))
 
 /// Converts packed RGB8 to packed RGB565.
 #define RGB8_to_565(r,g,b)  (((b)>>3)&0x1f)|((((g)>>2)&0x3f)<<5)|((((r)>>3)&0x1f)<<11)
diff --git a/include/hid.h b/include/hid.h
index 96e2a1f..11ae9bf 100644
--- a/include/hid.h
+++ b/include/hid.h
@@ -1,9 +1,10 @@
 #pragma once
 
 #include "types.h"
-#include "io.h"
 
 
+#define HID_KEY_MASK_ALL  ((KEY_Y << 1) - 1)
+
 
 enum
 {
@@ -21,7 +22,6 @@
 	KEY_Y       = (1<<11),
 };
 
-#define HID_KEY_MASK_ALL       ((KEY_Y << 1) - 1)
 
 
 void hidScanInput(void);
diff --git a/include/io.h b/include/io.h
deleted file mode 100644
index da617b6..0000000
--- a/include/io.h
+++ /dev/null
@@ -1,254 +0,0 @@
-#pragma once
-
-#include "types.h"
-#include "mem_map.h"
-
-
-
-#ifdef ARM9
-/* CFG */
-#define CFG_REGS_BASE            (IO_MEM_ARM9_ONLY)
-#define REG_CARDCONF             *((vu16*)(CFG_REGS_BASE + 0x0000C))
-#define REG_CARDCONF2            *((vu8* )(CFG_REGS_BASE + 0x00010))
-#define CFG_BOOTENV              *((vu32*)(CFG_REGS_BASE + 0x10000))
-#define CFG_UNITINFO             *((vu8* )(CFG_REGS_BASE + 0x10010))
-
-
-/* IRQ */
-#define IRQ_REGS_BASE            (IO_MEM_ARM9_ONLY + 0x1000)
-#define REG_IRQ_IE               *((vu32*)(IRQ_REGS_BASE + 0x00))
-#define REG_IRQ_IF               *((vu32*)(IRQ_REGS_BASE + 0x04))
-
-
-/* NDMA */
-#define NDMA_REGS_BASE           (IO_MEM_ARM9_ONLY + 0x2000)
-#define REG_NDMA_GLOBAL_CNT      *((vu32*)(NDMA_REGS_BASE + 0x00))
-
-#define REG_NDMA0_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x04))
-#define REG_NDMA0_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x08))
-#define REG_NDMA0_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x0C))
-#define REG_NDMA0_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x10))
-#define REG_NDMA0_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x14))
-#define REG_NDMA0_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x18))
-#define REG_NDMA0_CNT            *((vu32*)(NDMA_REGS_BASE + 0x1C))
-
-#define REG_NDMA1_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x20))
-#define REG_NDMA1_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x24))
-#define REG_NDMA1_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x28))
-#define REG_NDMA1_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x2C))
-#define REG_NDMA1_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x30))
-#define REG_NDMA1_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x34))
-#define REG_NDMA1_CNT            *((vu32*)(NDMA_REGS_BASE + 0x38))
-
-#define REG_NDMA2_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x3C))
-#define REG_NDMA2_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x40))
-#define REG_NDMA2_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x44))
-#define REG_NDMA2_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x48))
-#define REG_NDMA2_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x4C))
-#define REG_NDMA2_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x50))
-#define REG_NDMA2_CNT            *((vu32*)(NDMA_REGS_BASE + 0x54))
-
-#define REG_NDMA3_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x58))
-#define REG_NDMA3_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x5C))
-#define REG_NDMA3_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x60))
-#define REG_NDMA3_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x64))
-#define REG_NDMA3_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x68))
-#define REG_NDMA3_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x6C))
-#define REG_NDMA3_CNT            *((vu32*)(NDMA_REGS_BASE + 0x70))
-
-#define REG_NDMA4_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x74))
-#define REG_NDMA4_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x78))
-#define REG_NDMA4_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x7C))
-#define REG_NDMA4_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x80))
-#define REG_NDMA4_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0x84))
-#define REG_NDMA4_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0x88))
-#define REG_NDMA4_CNT            *((vu32*)(NDMA_REGS_BASE + 0x8C))
-
-#define REG_NDMA5_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x90))
-#define REG_NDMA5_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0x94))
-#define REG_NDMA5_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0x98))
-#define REG_NDMA5_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0x9C))
-#define REG_NDMA5_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xA0))
-#define REG_NDMA5_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xA4))
-#define REG_NDMA5_CNT            *((vu32*)(NDMA_REGS_BASE + 0xA8))
-
-#define REG_NDMA6_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xAC))
-#define REG_NDMA6_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xB0))
-#define REG_NDMA6_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0xB4))
-#define REG_NDMA6_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0xB8))
-#define REG_NDMA6_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xBC))
-#define REG_NDMA6_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xC0))
-#define REG_NDMA6_CNT            *((vu32*)(NDMA_REGS_BASE + 0xC4))
-
-#define REG_NDMA7_SRC_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xC8))
-#define REG_NDMA7_DST_ADDR       *((vu32*)(NDMA_REGS_BASE + 0xCC))
-#define REG_NDMA7_TRANSFER_CNT   *((vu32*)(NDMA_REGS_BASE + 0xD0))
-#define REG_NDMA7_WRITE_CNT      *((vu32*)(NDMA_REGS_BASE + 0xD4))
-#define REG_NDMA7_BLOCK_CNT      *((vu32*)(NDMA_REGS_BASE + 0xD8))
-#define REG_NDMA7_FILL_DATA      *((vu32*)(NDMA_REGS_BASE + 0xDC))
-#define REG_NDMA7_CNT            *((vu32*)(NDMA_REGS_BASE + 0xE0))
-
-#define REG_NDMA_SRC_ADDR(n)     *((vu32*)(NDMA_REGS_BASE + 0x04 + (n * 28)))
-#define REG_NDMA_DST_ADDR(n)     *((vu32*)(NDMA_REGS_BASE + 0x08 + (n * 28)))
-#define REG_NDMA_TRANSFER_CNT(n) *((vu32*)(NDMA_REGS_BASE + 0x0C + (n * 28)))
-#define REG_NDMA_WRITE_CNT(n)    *((vu32*)(NDMA_REGS_BASE + 0x10 + (n * 28)))
-#define REG_NDMA_BLOCK_CNT(n)    *((vu32*)(NDMA_REGS_BASE + 0x14 + (n * 28)))
-#define REG_NDMA_FILL_DATA(n)    *((vu32*)(NDMA_REGS_BASE + 0x18 + (n * 28)))
-#define REG_NDMA_CNT(n)          *((vu32*)(NDMA_REGS_BASE + 0x1C + (n * 28)))
-
-
-/* TIMER */
-#define TIMER_REGS_BASE          (IO_MEM_ARM9_ONLY + 0x3000)
-#define REG_TIMER0_VAL           *((vu16*)(TIMER_REGS_BASE + 0x00))
-#define REG_TIMER0_CNT           *((vu16*)(TIMER_REGS_BASE + 0x02))
-
-#define REG_TIMER1_VAL           *((vu16*)(TIMER_REGS_BASE + 0x04))
-#define REG_TIMER1_CNT           *((vu16*)(TIMER_REGS_BASE + 0x06))
-
-#define REG_TIMER2_VAL           *((vu16*)(TIMER_REGS_BASE + 0x08))
-#define REG_TIMER2_CNT           *((vu16*)(TIMER_REGS_BASE + 0x0A))
-
-#define REG_TIMER3_VAL           *((vu16*)(TIMER_REGS_BASE + 0x0C))
-#define REG_TIMER3_CNT           *((vu16*)(TIMER_REGS_BASE + 0x0E))
-
-#define REG_TIMER_VAL(n)         *((vu16*)(TIMER_REGS_BASE + 0x00 + (n * 4)))
-#define REG_TIMER_CNT(n)         *((vu16*)(TIMER_REGS_BASE + 0x02 + (n * 4)))
-
-
-/* CTRCARD */
-#define CTRCARD_REGS_BASE        (IO_MEM_ARM9_ONLY + 0x4000)
-#define REG_CTRCARDCNT           *((vu32*)(CTRCARD_REGS_BASE + 0x00))
-#define REG_CTRCARDBLKCNT        *((vu32*)(CTRCARD_REGS_BASE + 0x04))
-#define REG_CTRCARDSECCNT        *((vu32*)(CTRCARD_REGS_BASE + 0x08))
-#define REG_CTRCARDSECSEED       *((vu32*)(CTRCARD_REGS_BASE + 0x10))
-#define REG_CTRCARDCMD            ((vu32*)(CTRCARD_REGS_BASE + 0x20))
-#define REG_CTRCARDFIFO          *((vu32*)(CTRCARD_REGS_BASE + 0x30))
-
-
-/* EMMC */
-//#define EMMC_REGS_BASE           (IO_MEM_ARM9_ONLY + 0x6000)
-// Porting the eMMC driver every time is too much so
-// we leave the reg definitions in sdmmc.h
-
-
-/* PXI9 */
-#define PXI9_REGS_BASE           (IO_MEM_ARM9_ONLY + 0x8000)
-#define REG_PXI_SYNC9            *((vu32*)(PXI9_REGS_BASE + 0x00))
-#define REG_PXI_CNT9             *((vu32*)(PXI9_REGS_BASE + 0x04))
-#define REG_PXI_SEND9            *((vu32*)(PXI9_REGS_BASE + 0x08))
-#define REG_PXI_RECV9            *((vu32*)(PXI9_REGS_BASE + 0x0C))
-
-
-/* AES */
-#define AES_REGS_BASE            (IO_MEM_ARM9_ONLY + 0x9000)
-#define REG_AESCNT               *((vu32*)(AES_REGS_BASE + 0x000))
-#define REG_AESBLKCNT            *((vu32*)(AES_REGS_BASE + 0x004))
-#define REG_AESBLKCNTH1          *((vu16*)(AES_REGS_BASE + 0x004))
-#define REG_AESBLKCNTH2          *((vu16*)(AES_REGS_BASE + 0x006))
-#define REG_AESWRFIFO             ((vu32*)(AES_REGS_BASE + 0x008))
-#define REG_AESRDFIFO             ((vu32*)(AES_REGS_BASE + 0x00C))
-#define REG_AESKEYSEL            *((vu8* )(AES_REGS_BASE + 0x010))
-#define REG_AESKEYCNT            *((vu8* )(AES_REGS_BASE + 0x011))
-#define REG_AESCTR                ((vu32*)(AES_REGS_BASE + 0x020))
-#define REG_AESMAC                ((vu32*)(AES_REGS_BASE + 0x030))
-
-#define REG_AESKEY0               ((vu32*)(AES_REGS_BASE + 0x040))
-#define REG_AESKEYX0              ((vu32*)(AES_REGS_BASE + 0x050))
-#define REG_AESKEYY0              ((vu32*)(AES_REGS_BASE + 0x060))
-#define REG_AESKEY1               ((vu32*)(AES_REGS_BASE + 0x070))
-#define REG_AESKEYX1              ((vu32*)(AES_REGS_BASE + 0x080))
-#define REG_AESKEYY1              ((vu32*)(AES_REGS_BASE + 0x090))
-#define REG_AESKEY2               ((vu32*)(AES_REGS_BASE + 0x0A0))
-#define REG_AESKEYX2              ((vu32*)(AES_REGS_BASE + 0x0B0))
-#define REG_AESKEYY2              ((vu32*)(AES_REGS_BASE + 0x0C0))
-#define REG_AESKEY3               ((vu32*)(AES_REGS_BASE + 0x0D0))
-#define REG_AESKEYX3              ((vu32*)(AES_REGS_BASE + 0x0E0))
-#define REG_AESKEYY3              ((vu32*)(AES_REGS_BASE + 0x0F0))
-
-#define REG_AESKEYFIFO            ((vu32*)(AES_REGS_BASE + 0x100))
-#define REG_AESKEYXFIFO           ((vu32*)(AES_REGS_BASE + 0x104))
-#define REG_AESKEYYFIFO           ((vu32*)(AES_REGS_BASE + 0x108))
-
-
-/* SHA */
-#define SHA_REGS_BASE            (IO_MEM_ARM9_ONLY + 0xA000)
-#define REG_SHA_CNT              *((vu32*)(SHA_REGS_BASE + 0x00))
-#define REG_SHA_BLKCNT           *((vu32*)(SHA_REGS_BASE + 0x04))
-#define REG_SHA_HASH              ((u32* )(SHA_REGS_BASE + 0x40))
-#define REG_SHA_INFIFO            (       (SHA_REGS_BASE + 0x80))
-
-
-/* PRNG */
-#define PRNG_REGS_BASE           (IO_MEM_ARM9_ONLY + 0x11000)
-#define REG_PRNG                  ((vu32*)(PRNG_REGS_BASE))
-
-
-/* OTP */
-#define OTP_REGS_BASE            (IO_MEM_ARM9_ONLY + 0x12000)
-#define REG_OTP                   ((vu32*)(OTP_REGS_BASE))
-#endif
-
-
-/* PDN */
-#define PDN_REGS_BASE            (IO_MEM_ARM9_ARM11 + 0x40000)
-#define REG_PDN_GPU_CNT          *((vu32*)(PDN_REGS_BASE + 0x1200))
-#define REG_PDN_GPU_CNT2         *((vu32*)(PDN_REGS_BASE + 0x1204))
-#define REG_PDN_GPU_CNT2_8BIT    *((vu8* )(PDN_REGS_BASE + 0x1204))
-#define REG_PDN_GPU_CNT4         *((vu8* )(PDN_REGS_BASE + 0x1208))
-#define REG_PDN_GPU_CNT3         *((vu16*)(PDN_REGS_BASE + 0x1210))
-#define REG_PDN_MPCORE_CLKCNT    *((vu16*)(PDN_REGS_BASE + 0x1300))
-
-
-#define HID_REGS_BASE            (IO_MEM_ARM9_ARM11 + 0x00046000)
-#define REG_HID_PAD              ~(*((vu32*)(HID_REGS_BASE)))
-
-
-/* SPI */
-#define SPI_REGS_BUS2_BASE       (IO_MEM_ARM9_ARM11 + 0x60000)
-#define REG_SPI_BUS2_CNT         *((vu16*)(SPI_REGS_BUS2_BASE + 0x00))
-#define REG_SPI_BUS2_DATA        *((vu8* )(SPI_REGS_BUS2_BASE + 0x02))
-
-
-/* PXI11 */
-#define PXI11_REGS_BASE          (IO_MEM_ARM9_ARM11 + 0x63000)
-#define REG_PXI_SYNC11           *((vu32*)(PXI11_REGS_BASE + 0x00))
-#define REG_PXI_CNT11            *((vu32*)(PXI11_REGS_BASE + 0x04))
-#define REG_PXI_SEND11           *((vu32*)(PXI11_REGS_BASE + 0x08))
-#define REG_PXI_RECV11           *((vu32*)(PXI11_REGS_BASE + 0x0C))
-
-
-/* NTRCARD */
-#define NTRCARD_REGS_BASE        (IO_MEM_ARM9_ARM11 + 0x64000)
-#define REG_NTRCARDMCNT          *((vu16*)(NTRCARD_REGS_BASE + 0x00))
-#define REG_NTRCARDMDATA         *((vu16*)(NTRCARD_REGS_BASE + 0x02))
-#define REG_NTRCARDROMCNT        *((vu32*)(NTRCARD_REGS_BASE + 0x04))
-#define REG_NTRCARDCMD            ((vu8* )(NTRCARD_REGS_BASE + 0x08))
-#define REG_NTRCARDSEEDX_L       *((vu32*)(NTRCARD_REGS_BASE + 0x10))
-#define REG_NTRCARDSEEDY_L       *((vu32*)(NTRCARD_REGS_BASE + 0x14))
-#define REG_NTRCARDSEEDX_H       *((vu16*)(NTRCARD_REGS_BASE + 0x18))
-#define REG_NTRCARDSEEDY_H       *((vu16*)(NTRCARD_REGS_BASE + 0x1A))
-#define REG_NTRCARDFIFO          *((vu32*)(NTRCARD_REGS_BASE + 0x1C))
-
-
-/* I2C */
-#define I2C_REGS_BUS0_BASE       (IO_MEM_ARM9_ARM11 + 0x61000)
-#define I2C_REGS_BUS1_BASE       (IO_MEM_ARM9_ARM11 + 0x44000)
-#define REG_I2C_BUS0_DATA        *((vu8* )(I2C_REGS_BUS0_BASE + 0x00))
-#define REG_I2C_BUS1_DATA        *((vu8* )(I2C_REGS_BUS1_BASE + 0x00))
-#define REG_I2C_BUS0_CNT         *((vu8* )(I2C_REGS_BUS0_BASE + 0x01))
-#define REG_I2C_BUS1_CNT         *((vu8* )(I2C_REGS_BUS1_BASE + 0x01))
-
-
-#ifdef ARM11
-/* LCD */
-#define LCD_REGS_BASE            (IO_MEM_ARM11_ONLY + 0x2000)
-#define REG_LCD_COLORFILL_MAIN   *((vu32*)(LCD_REGS_BASE + 0x204))
-#define REG_LCD_COLORFILL_SUB    *((vu32*)(LCD_REGS_BASE + 0xA04))
-#define REG_LCD_BACKLIGHT_MAIN   *((vu32*)(LCD_REGS_BASE + 0x240))
-#define REG_LCD_BACKLIGHT_SUB    *((vu32*)(LCD_REGS_BASE + 0xA40))
-
-
-/* GPU External Registers */
-#define GPU_EXT_REGS_BASE        (IO_MEM_ARM11_ONLY + 0x200000)
-#define REG_GPU_EXT_CNT          *((vu32*)(GPU_EXT_REGS_BASE + 0x04))
-#endif
diff --git a/include/pxi.h b/include/pxi.h
index 474dcfe..1fb382e 100644
--- a/include/pxi.h
+++ b/include/pxi.h
@@ -1,7 +1,25 @@
 #pragma once
 
+#include "mem_map.h"
 #include "types.h"
-#include "io.h"
+
+
+#ifdef ARM9
+#define PXI9_REGS_BASE              (IO_MEM_ARM9_ONLY + 0x8000)
+#define REG_PXI_SYNC9               *((vu32*)(PXI9_REGS_BASE + 0x00))
+#define REG_PXI_CNT9                *((vu32*)(PXI9_REGS_BASE + 0x04))
+#define REG_PXI_SEND9               *((vu32*)(PXI9_REGS_BASE + 0x08))
+#define REG_PXI_RECV9               *((vu32*)(PXI9_REGS_BASE + 0x0C))
+#endif
+
+#ifdef ARM11
+#define PXI11_REGS_BASE             (IO_MEM_ARM9_ARM11 + 0x63000)
+#define REG_PXI_SYNC11              *((vu32*)(PXI11_REGS_BASE + 0x00))
+#define REG_PXI_CNT11               *((vu32*)(PXI11_REGS_BASE + 0x04))
+#define REG_PXI_SEND11              *((vu32*)(PXI11_REGS_BASE + 0x08))
+#define REG_PXI_RECV11              *((vu32*)(PXI11_REGS_BASE + 0x0C))
+#endif
+
 
 // Defines for PX_SYNC regs
 #define PXI_DATA_RECEIVED(reg)      (reg & 0xFF)
diff --git a/source/arm11/gfx.c b/source/arm11/gfx.c
index 2e67efa..d018aad 100644
--- a/source/arm11/gfx.c
+++ b/source/arm11/gfx.c
@@ -1,11 +1,27 @@
-#include "types.h"
-#include "IO.h"
 #include "mem_map.h"
+#include "types.h"
 #include "util.h"
 #include "arm11/i2c.h"
 #include "gfx.h"
 
 
+#define PDN_REGS_BASE            (IO_MEM_ARM9_ARM11 + 0x40000)
+#define REG_PDN_GPU_CNT          *((vu32*)(PDN_REGS_BASE + 0x1200))
+#define REG_PDN_GPU_CNT2         *((vu32*)(PDN_REGS_BASE + 0x1204))
+#define REG_PDN_GPU_CNT2_8BIT    *((vu8* )(PDN_REGS_BASE + 0x1204))
+#define REG_PDN_GPU_CNT4         *((vu8* )(PDN_REGS_BASE + 0x1208))
+#define REG_PDN_GPU_CNT3         *((vu16*)(PDN_REGS_BASE + 0x1210))
+
+#define LCD_REGS_BASE           (IO_MEM_ARM11_ONLY + 0x2000)
+#define REG_LCD_COLORFILL_MAIN  *((vu32*)(LCD_REGS_BASE + 0x204))
+#define REG_LCD_COLORFILL_SUB   *((vu32*)(LCD_REGS_BASE + 0xA04))
+#define REG_LCD_BACKLIGHT_MAIN  *((vu32*)(LCD_REGS_BASE + 0x240))
+#define REG_LCD_BACKLIGHT_SUB   *((vu32*)(LCD_REGS_BASE + 0xA40))
+
+#define GPU_EXT_REGS_BASE       (IO_MEM_ARM11_ONLY + 0x200000)
+#define REG_GPU_EXT_CNT         *((vu32*)(GPU_EXT_REGS_BASE + 0x04))
+
+
 
 extern void gpio_set_bit(vu16 *reg, u8 bit_num);
 extern void gpio_clear_bit(vu16 *reg, u8 bit_num);
diff --git a/source/arm11/i2c.c b/source/arm11/i2c.c
index 365c3f6..1a57361 100644
--- a/source/arm11/i2c.c
+++ b/source/arm11/i2c.c
@@ -1,15 +1,22 @@
-#include "types.h"
-#include "IO.h"
 #include "mem_map.h"
+#include "types.h"
 #include "util.h"
 
 
+#define I2C_REGS_BUS0_BASE  (IO_MEM_ARM9_ARM11 + 0x61000)
+#define I2C_REGS_BUS1_BASE  (IO_MEM_ARM9_ARM11 + 0x44000)
+#define REG_I2C_BUS0_DATA   *((vu8* )(I2C_REGS_BUS0_BASE + 0x00))
+#define REG_I2C_BUS1_DATA   *((vu8* )(I2C_REGS_BUS1_BASE + 0x00))
+#define REG_I2C_BUS0_CNT    *((vu8* )(I2C_REGS_BUS0_BASE + 0x01))
+#define REG_I2C_BUS1_CNT    *((vu8* )(I2C_REGS_BUS1_BASE + 0x01))
+
 
 struct i2c_dev_table_entry {
 	u32 bus_id;
 	u8 devaddr;
 };
 
+
 static const struct i2c_dev_table_entry i2c_dev_table[] =
 {
 	{0,	0x4A},
@@ -23,7 +30,6 @@
 	{1,	0x44}
 };
 
-
 // i2c mcu defines
 bool i2cmcu_reg0_upper_read;
 u8 i2cmcu_reg0_upper_data;
@@ -32,6 +38,7 @@
 u8 i2cmcu_readreg0x0_bus0_second;
 
 
+
 void i2c_wait(u32 bus_id);
 void i2c_put_byte(u32 bus_id, u8 data_byte);
 void i2c_start(u32 bus_id);
diff --git a/source/arm9/crypto.c b/source/arm9/crypto.c
index 435e96f..82b3c27 100644
--- a/source/arm9/crypto.c
+++ b/source/arm9/crypto.c
@@ -7,8 +7,8 @@
 
 #include <assert.h>
 #include <string.h>
-#include "types.h"
 #include "mem_map.h"
+#include "types.h"
 #include "arm9/crypto.h"
 #include "arm9/interrupt.h"
 #include "arm9/ndma.h"
@@ -20,6 +20,36 @@
 //             AES              //
 //////////////////////////////////
 
+#define AES_REGS_BASE    (IO_MEM_ARM9_ONLY + 0x9000)
+#define REG_AESCNT       *((vu32*)(AES_REGS_BASE + 0x000))
+#define REG_AESBLKCNT    *((vu32*)(AES_REGS_BASE + 0x004))
+#define REG_AESBLKCNTH1  *((vu16*)(AES_REGS_BASE + 0x004))
+#define REG_AESBLKCNTH2  *((vu16*)(AES_REGS_BASE + 0x006))
+#define REG_AESWRFIFO     ((vu32*)(AES_REGS_BASE + 0x008))
+#define REG_AESRDFIFO     ((vu32*)(AES_REGS_BASE + 0x00C))
+#define REG_AESKEYSEL    *((vu8* )(AES_REGS_BASE + 0x010))
+#define REG_AESKEYCNT    *((vu8* )(AES_REGS_BASE + 0x011))
+#define REG_AESCTR        ((vu32*)(AES_REGS_BASE + 0x020))
+#define REG_AESMAC        ((vu32*)(AES_REGS_BASE + 0x030))
+
+#define REG_AESKEY0       ((vu32*)(AES_REGS_BASE + 0x040))
+#define REG_AESKEYX0      ((vu32*)(AES_REGS_BASE + 0x050))
+#define REG_AESKEYY0      ((vu32*)(AES_REGS_BASE + 0x060))
+#define REG_AESKEY1       ((vu32*)(AES_REGS_BASE + 0x070))
+#define REG_AESKEYX1      ((vu32*)(AES_REGS_BASE + 0x080))
+#define REG_AESKEYY1      ((vu32*)(AES_REGS_BASE + 0x090))
+#define REG_AESKEY2       ((vu32*)(AES_REGS_BASE + 0x0A0))
+#define REG_AESKEYX2      ((vu32*)(AES_REGS_BASE + 0x0B0))
+#define REG_AESKEYY2      ((vu32*)(AES_REGS_BASE + 0x0C0))
+#define REG_AESKEY3       ((vu32*)(AES_REGS_BASE + 0x0D0))
+#define REG_AESKEYX3      ((vu32*)(AES_REGS_BASE + 0x0E0))
+#define REG_AESKEYY3      ((vu32*)(AES_REGS_BASE + 0x0F0))
+
+#define REG_AESKEYFIFO    ((vu32*)(AES_REGS_BASE + 0x100))
+#define REG_AESKEYXFIFO   ((vu32*)(AES_REGS_BASE + 0x104))
+#define REG_AESKEYYFIFO   ((vu32*)(AES_REGS_BASE + 0x108))
+
+
 // TODO: Handle endianess!
 static void addCounter(u32 *restrict ctr, u32 val)
 {
@@ -242,6 +272,13 @@
 //             SHA              //
 //////////////////////////////////
 
+#define SHA_REGS_BASE   (IO_MEM_ARM9_ONLY + 0xA000)
+#define REG_SHA_CNT     *((vu32*)(SHA_REGS_BASE + 0x00))
+#define REG_SHA_BLKCNT  *((vu32*)(SHA_REGS_BASE + 0x04))
+#define REG_SHA_HASH     ((u32* )(SHA_REGS_BASE + 0x40))
+#define REG_SHA_INFIFO   (       (SHA_REGS_BASE + 0x80))
+
+
 void SHA_start(u32 params)
 {
 	REG_SHA_CNT = SHA_ENABLE | params;
diff --git a/source/arm9/main.c b/source/arm9/main.c
index 998234d..44b4004 100644
--- a/source/arm9/main.c
+++ b/source/arm9/main.c
@@ -1,6 +1,8 @@
 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
+#include "mem_map.h"
+#include "types.h"
 #include "util.h"
 #include "pxi.h"
 #include "hid.h"
@@ -13,6 +15,8 @@
 #include "arm9/menu.h"
 #include "arm9/main.h"
 
+
+
 static bool devs_init();
 static bool fs_early_init();
 static bool mount_fs();
@@ -258,6 +262,9 @@
 	}
 }
 
+#define PDN_REGS_BASE          (IO_MEM_ARM9_ARM11 + 0x40000)
+#define REG_PDN_MPCORE_CLKCNT  *((vu16*)(PDN_REGS_BASE + 0x1300))
+
 static void unit_detect()
 {
 	bootInfo.unit_is_new3ds = REG_PDN_MPCORE_CLKCNT != 0;
@@ -267,6 +274,10 @@
 	printf("%s detected!\n", bootInfo.model);
 }
 
+#define CFG_REGS_BASE          (IO_MEM_ARM9_ONLY)
+#define CFG_BOOTENV            *((vu32*)(CFG_REGS_BASE + 0x10000))
+#define CFG_UNITINFO           *((vu8* )(CFG_REGS_BASE + 0x10010))
+
 static void boot_env_detect()
 {
 	static const char *boot_environment [4]	=	{	"Cold boot",				// 0
@@ -321,6 +332,9 @@
 	return false;
 }
 
+#define PRNG_REGS_BASE  (IO_MEM_ARM9_ONLY + 0x11000)
+#define REG_PRNG         ((vu32*)(PRNG_REGS_BASE))
+
 u8 rng_get_byte()
 {
 	u32 tmp = REG_PRNG[0];
diff --git a/source/arm9/menu.c b/source/arm9/menu.c
index cb7126c..2a140e7 100644
--- a/source/arm9/menu.c
+++ b/source/arm9/menu.c
@@ -3,7 +3,6 @@
 #include <string.h>
 #include "types.h"
 #include "mem_map.h"
-#include "io.h"
 #include "util.h"
 #include "pxi.h"
 #include "arm9/console.h"
diff --git a/source/arm9/ndma.c b/source/arm9/ndma.c
index 86f87a7..059f468 100644
--- a/source/arm9/ndma.c
+++ b/source/arm9/ndma.c
@@ -5,7 +5,6 @@
 
 #include <assert.h>
 #include "types.h"
-#include "mem_map.h"
 #include "arm9/ndma.h"
 #include "arm9/interrupt.h"
 
diff --git a/source/arm9/spiflash.c b/source/arm9/spiflash.c
index 9d473d7..bab3017 100644
--- a/source/arm9/spiflash.c
+++ b/source/arm9/spiflash.c
@@ -1,8 +1,13 @@
+#include "mem_map.h"
 #include "types.h"
-#include "io.h"
 #include "arm9/spiflash.h"
 
 
+#define SPI_REGS_BUS2_BASE  (IO_MEM_ARM9_ARM11 + 0x60000)
+#define REG_SPI_BUS2_CNT    *((vu16*)(SPI_REGS_BUS2_BASE + 0x00))
+#define REG_SPI_BUS2_DATA   *((vu8* )(SPI_REGS_BUS2_BASE + 0x02))
+
+
 
 static void spi_busy_wait()
 {
diff --git a/source/arm9/timer.c b/source/arm9/timer.c
index ead2ece..4131464 100644
--- a/source/arm9/timer.c
+++ b/source/arm9/timer.c
@@ -1,8 +1,26 @@
+#include "mem_map.h"
 #include "types.h"
 #include "arm9/timer.h"
 #include "arm9/interrupt.h"
 
 
+#define TIMER_REGS_BASE   (IO_MEM_ARM9_ONLY + 0x3000)
+#define REG_TIMER0_VAL    *((vu16*)(TIMER_REGS_BASE + 0x00))
+#define REG_TIMER0_CNT    *((vu16*)(TIMER_REGS_BASE + 0x02))
+
+#define REG_TIMER1_VAL    *((vu16*)(TIMER_REGS_BASE + 0x04))
+#define REG_TIMER1_CNT    *((vu16*)(TIMER_REGS_BASE + 0x06))
+
+#define REG_TIMER2_VAL    *((vu16*)(TIMER_REGS_BASE + 0x08))
+#define REG_TIMER2_CNT    *((vu16*)(TIMER_REGS_BASE + 0x0A))
+
+#define REG_TIMER3_VAL    *((vu16*)(TIMER_REGS_BASE + 0x0C))
+#define REG_TIMER3_CNT    *((vu16*)(TIMER_REGS_BASE + 0x0E))
+
+#define REG_TIMER_VAL(n)  *((vu16*)(TIMER_REGS_BASE + 0x00 + (n * 4)))
+#define REG_TIMER_CNT(n)  *((vu16*)(TIMER_REGS_BASE + 0x02 + (n * 4)))
+
+
 
 void TIMER_init(void)
 {
diff --git a/source/hid.c b/source/hid.c
index 54303f3..1ab8bb5 100644
--- a/source/hid.c
+++ b/source/hid.c
@@ -2,9 +2,15 @@
  *  Original code from ctrulib
  */
 
+#include "mem_map.h"
 #include "types.h"
 #include "hid.h"
 
+
+#define HID_REGS_BASE  (IO_MEM_ARM9_ARM11 + 0x00046000)
+#define REG_HID_PAD    ~(*((vu32*)(HID_REGS_BASE)))
+
+
 static u32 kOld, kHeld, kDown, kUp;