diff --git a/Makefile.arm11 b/Makefile.arm11
index 454f232..2c40a3f 100644
--- a/Makefile.arm11
+++ b/Makefile.arm11
@@ -29,7 +29,7 @@
 
 LDNAME	:=	arm11.ld
 
-ARCH	:=	-march=armv6k -mtune=mpcore -mfloat-abi=soft -marm -mthumb-interwork
+ARCH	:=	-march=armv6k -mtune=mpcore -mfloat-abi=hard -marm -mthumb-interwork
 
 DBGWARM	:=	-Wextra -Wcast-align -Wcast-qual -Wdisabled-optimization \
 			-Wformat=2 -Wlogical-op -Wmissing-include-dirs -Wredundant-decls \
diff --git a/source/arm11/cache.s b/source/arm11/cache.s
index 2578602..c124530 100644
--- a/source/arm11/cache.s
+++ b/source/arm11/cache.s
@@ -1,6 +1,6 @@
 .arm
 .cpu mpcore
-.fpu softvfp
+.fpu vfpv2
 
 .global invalidateICache
 .global flushDCache
diff --git a/source/arm11/cpu.s b/source/arm11/cpu.s
index 006391f..2fedad4 100644
--- a/source/arm11/cpu.s
+++ b/source/arm11/cpu.s
@@ -2,13 +2,14 @@
 
 .arm
 .cpu mpcore
-.fpu softvfp
+.fpu vfpv2
 
 .global initCpu
 .global deinitCpu
 
 .type initCpu STT_FUNC
 .type setupExceptionVectors STT_FUNC
+.type setupVfp STT_FUNC
 .type deinitCpu STT_FUNC
 
 .extern setupMmu
@@ -49,6 +50,7 @@
 	ldr sp, =A11_STACK_END
 
 	bl setupExceptionVectors    @ Setup the vectors in AXIWRAM bootrom vectors jump to
+	bl setupVfp
 	blx setupMmu
 	bx r10
 .pool
@@ -80,6 +82,19 @@
 	.word 0
 
 
+setupVfp:
+	mov r0, #0
+	mov r1, #0x00F00000         @ Give full access to cp10/11 in user and privileged mode
+	mcr p15, 0, r1, c1, c0, 2   @ Write Coprocessor Access Control Register
+	mcr p15, 0, r0, c7, c5, 4   @ Flush Prefetch Buffer
+	mov r1, #0x40000000         @ Clear exception bits and enable VFP11
+	mov r2, #0x03C00000         @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode
+	fmxr fpexc, r1              @ Write Floating-point exception register
+	fmxr fpscr, r2              @ Write Floating-Point Status and Control Register
+	bx lr
+.pool
+
+
 deinitCpu:
 	mov r4, lr
 
@@ -93,6 +108,7 @@
 		bne deinitCpu_vector_lp
 
 	bl flushDCache
+	mov r2, #0
 	mrc p15, 0, r0, c1, c0, 0   @ Read control register
 	ldr r1, =0x803805           @ MMU, D-Cache, Program flow prediction, I-Cache,
                                 @ high exception vectors, subpage AP bits disabled
@@ -104,10 +120,12 @@
                                 @ SMP mode: the CPU is taking part in coherency and L1 parity checking
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
 
-	mov r0, #0
-	mcr p15, 0, r0, c7, c5, 4   @ Flush Prefetch Buffer
-	mcr p15, 0, r0, c7, c7, 0   @ Invalidate Both Caches. Also flushes the branch target cache
-	mcr p15, 0, r0, c7, c10, 4  @ Data Synchronization Barrier
+	mcr p15, 0, r2, c7, c5, 4   @ Flush Prefetch Buffer
+	mcr p15, 0, r2, c7, c7, 0   @ Invalidate Both Caches. Also flushes the branch target cache
+	mcr p15, 0, r2, c7, c10, 4  @ Data Synchronization Barrier
 	clrex
+	@ Disable VFP11
+	fmxr fpscr, r2              @ Write Floating-Point Status and Control Register
+	fmxr fpexc, r2              @ Write Floating-point exception register
 	bx r4
 .pool
diff --git a/source/arm11/gpio.s b/source/arm11/gpio.s
index 405761f..72b9e0c 100644
--- a/source/arm11/gpio.s
+++ b/source/arm11/gpio.s
@@ -1,6 +1,6 @@
 .arm
 .cpu mpcore
-.fpu softvfp
+.fpu vfpv2
 
 .global gpio_set_bit
 .global gpio_clear_bit
diff --git a/source/arm11/mmu.c b/source/arm11/mmu.c
index 4f2c352..5baac7f 100644
--- a/source/arm11/mmu.c
+++ b/source/arm11/mmu.c
@@ -84,18 +84,14 @@
 
 void setupMmu(void)
 {
-	// Give full access to all non-cp15 coprocessors
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 2\n\t" : : "r" (0xF00000u));
-	// Base AXIWRAM, Nonshared page table walk and outer cachable write-back cached, write allocate
-	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 0\n\t" : : "r" (A11_MMU_TABLES_BASE | 8u));
+	// TTBR0 address shared page table walk and outer cachable write-through, no allocate on write
+	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 0\n\t" : : "r" (A11_MMU_TABLES_BASE | 0x12u));
 	// Use the 16 KB L1 table only
 	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 2\n\t" : : "r" (0u));
 	// Domain 1 = client, remaining domains all = no access
 	__asm__ __volatile__("mcr p15, 0, %0, c3, c0, 0\n\t" : : "r" (4u));
 	// Context ID Register (ASID = 0, PROCID = 0)
 	__asm__ __volatile__("mcr p15, 0, %0, c13, c0, 1\n\t" : : "r" (0u));
-	// Thread ID Register (user and privileged read/write access) (Thread ID = 0)
-	__asm__ __volatile__("mcr p15, 0, %0, c13, c0, 2\n\t" : : "r" (0u));
 
 
 	// Clear L1 and L2 tables
@@ -150,7 +146,11 @@
 
 	// Modify Control Register
 	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r" (tmp) : );
-	tmp |= 0x803805u; // Enable MMU, D-Cache, Program flow prediction, I-Cache,
-	                  // high exception vectors, subpage AP bits disabled
+	tmp |= 0x803807u; // Enable MMU, Strict data address alignment fault, D-Cache,
+	                  // Program flow prediction, I-Cache, high exception vectors,
+	                  // subpage AP bits disabled
 	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r" (tmp));
+
+	// Flush Prefetch Buffer
+	__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4\n\t" : : "r" (0u));
 }
diff --git a/source/arm11/start.s b/source/arm11/start.s
index 15978d2..0231846 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -1,6 +1,6 @@
 .arm
 .cpu mpcore
-.fpu softvfp
+.fpu vfpv2
 
 .global _start
 .global clearMem
diff --git a/source/arm9/pxi.c b/source/arm9/pxi.c
index b47c087..428b2a9 100644
--- a/source/arm9/pxi.c
+++ b/source/arm9/pxi.c
@@ -11,6 +11,8 @@
 
 	REG_PXI_SYNC9 |= 9u<<8;
 	while((REG_PXI_SYNC9 & 0xFFu) != 11u);
+
+	REG_IRQ_IE |= (IRQ_PXI_SYNC | IRQ_PXI_NOT_FULL | IRQ_PXI_NOT_EMPTY);
 }
 
 void PXI_sendWord(u32 val)