diff --git a/source/arm11/mmu.c b/source/arm11/mmu.c
index 94bf5ba..8a27eaf 100644
--- a/source/arm11/mmu.c
+++ b/source/arm11/mmu.c
@@ -148,8 +148,8 @@
 
 	// Modify Control Register
 	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0" : "=r" (tmp) : );
-	tmp |= 0x803807u; // Enable MMU, Strict data address alignment fault, D-Cache,
-	                  // Program flow prediction, I-Cache, high exception vectors,
+	tmp |= 0xC03805u; // Enable MMU, D-Cache, Program flow prediction,
+	                  // I-Cache, high exception vectors, Unaligned data access,
 	                  // subpage AP bits disabled
 	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0" : : "r" (tmp));
 }
diff --git a/source/arm11/start.s b/source/arm11/start.s
index a7cea61..d2d9611 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -172,8 +172,8 @@
 	bl flushDCache
 	mov r2, #0
 	mrc p15, 0, r0, c1, c0, 0   @ Read control register
-	ldr r1, =0x803807           @ Enable MMU, Strict data address alignment fault, D-Cache,
-	                            @ Program flow prediction, I-Cache, high exception vectors,
+	ldr r1, =0xC03805           @ Disable MMU, D-Cache, Program flow prediction, I-Cache,
+	                            @ high exception vectors, Unaligned data access,
 	                            @ subpage AP bits disabled
 	bic r0, r0, r1
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register