diff --git a/include/arm.h b/include/arm.h
new file mode 100644
index 0000000..699ccbc
--- /dev/null
+++ b/include/arm.h
@@ -0,0 +1,230 @@
+#pragma once
+
+/*
+ *   This file is part of fastboot 3DS
+ *   Copyright (C) 2017 derrek, profi200
+ *
+ *   This program is free software: you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation, either version 3 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if !__ASSEMBLER__
+	#include "types.h"
+#endif
+
+
+// Program status register (CPSR/SPSR)
+#define PSR_USER_MODE   (16)
+#define PSR_FIQ_MODE    (17)
+#define PSR_IRQ_MODE    (18)
+#define PSR_SVC_MODE    (19)
+#define PSR_ABORT_MODE  (23)
+#define PSR_UNDEF_MODE  (27)
+#define PSR_SYS_MODE    (31)
+#define PSR_MODE_MASK   (PSR_SYS_MODE)
+
+#define PSR_T           (1<<5)          // Thumb mode
+#define PSR_F           (1<<6)          // Interrupts (FIQ) disable flag
+#define PSR_I           (1<<7)          // Interrupts (IRQ) disable flag
+#define PSR_A           (1<<8)          // Imprecise aborts disable flag
+#define PSR_E           (1<<9)          // Big endian
+#define PSR_J           (1<<24)         // Jazelle mode
+#define PSR_Q           (1<<27)
+#define PSR_V           (1<<28)         // Overflow flag
+#define PSR_C           (1<<29)         // Carry flag
+#define PSR_Z           (1<<30)         // Zero flag
+#define PSR_N           (1<<31)         // Negative flag
+#define PSR_INT_OFF     (PSR_I | PSR_F) // IRQ and FIQ disabled flags
+
+
+
+#if !__ASSEMBLER__
+
+#ifdef ARM11
+
+#define __cpsid(flags) __asm__ volatile("cpsid " #flags : : : "memory");
+#define __cpsie(flags) __asm__ volatile("cpsie " #flags : : : "memory");
+
+static inline void __wfi(void)
+{
+	__asm__ volatile("wfi" : : : "memory");
+}
+
+static inline void __wfe(void)
+{
+	__asm__ volatile("wfe" : : : "memory");
+}
+
+static inline void __sev(void)
+{
+	__asm__ volatile("sev" : : : "memory");
+}
+
+static inline void __isb(void)
+{
+	// Flush Prefetch Buffer
+	__asm__ volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory");
+}
+
+static inline void __dsb(void)
+{
+	__asm__ volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory");
+}
+
+static inline void __dmb(void)
+{
+	__asm__ volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory");
+}
+
+static inline u32 __getCpuId(void)
+{
+	u32 cpuId;
+	__asm__("mrc p15, 0, %0, c0, c0, 5" : "=r" (cpuId) : );
+	return cpuId & 3;
+}
+
+// Control Register
+static inline u32 __getCr(void)
+{
+	u32 cr;
+	__asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (cr) : );
+	return cr;
+}
+
+static inline void __setCr(u32 cr)
+{
+	__asm__ volatile("mcr p15, 0, %0, c1, c0, 0" : : "r" (cr) : "memory");
+}
+
+// Auxiliary Control Register
+static inline u32 __getAcr(void)
+{
+	u32 acr;
+	__asm__("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr) : );
+	return acr;
+}
+
+static inline void __setAcr(u32 acr)
+{
+	__asm__ volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr) : "memory");
+}
+
+// Translation Table Base Register 0
+static inline u32 __getTtbr0(void)
+{
+	u32 ttb0;
+	__asm__("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb0) : );
+	return ttb0;
+}
+
+static inline void __setTtbr0(u32 ttb0)
+{
+	__asm__ volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb0) : "memory");
+}
+
+// Translation Table Base Register 1
+static inline u32 __getTtbr1(void)
+{
+	u32 ttb1;
+	__asm__("mrc p15, 0, %0, c2, c0, 1" : "=r" (ttb1) : );
+	return ttb1;
+}
+
+static inline void __setTtbr1(u32 ttb1)
+{
+	__asm__ volatile("mcr p15, 0, %0, c2, c0, 1" : : "r" (ttb1) : "memory");
+}
+
+// Translation Table Base Control Register
+static inline u32 __getTtbcr(void)
+{
+	u32 ttbcr;
+	__asm__("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr) : );
+	return ttbcr;
+}
+
+static inline void __setTtbcr(u32 ttbcr)
+{
+	__asm__ volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr) : "memory");
+}
+
+// Domain Access Control Register
+static inline u32 __getDacr(void)
+{
+	u32 dacr;
+	__asm__("mrc p15, 0, %0, c3, c0, 0" : "=r" (dacr) : );
+	return dacr;
+}
+
+static inline void __setDacr(u32 dacr)
+{
+	__asm__ volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr) : "memory");
+}
+
+// Context ID Register
+static inline u32 __getCidr(void)
+{
+	u32 cidr;
+	__asm__("mrc p15, 0, %0, c13, c0, 1" : "=r" (cidr) : );
+	return cidr;
+}
+
+static inline void __setCidr(u32 cidr)
+{
+	__asm__ volatile("mcr p15, 0, %0, c13, c0, 1" : : "r" (cidr) : "memory");
+}
+
+#elif ARM9
+
+static inline void __wfi(void)
+{
+	__asm__ volatile("mcr p15, 0, %0, c7, c0, 4" : : "r" (0) : "memory");
+}
+
+#endif // ifdef ARM11, elif ARM9
+
+static inline u32 __getCpsr(void)
+{
+	u32 cpsr;
+	__asm__("mrs %0, cpsr" : "=r" (cpsr) : );
+	return cpsr;
+}
+
+static inline void __setCpsr_c(u32 cpsr)
+{
+	__asm__ volatile("msr cpsr_c, %0" : : "r" (cpsr) : "memory");
+}
+
+static inline void __setCpsr(u32 cpsr)
+{
+	__asm__ volatile("msr cpsr_cxsf, %0" : : "r" (cpsr) : "memory");
+}
+
+static inline u32 __getSpsr(void)
+{
+	u32 spsr;
+	__asm__("mrs %0, spsr" : "=r" (spsr) : );
+	return spsr;
+}
+
+static inline void __setSpsr_c(u32 spsr)
+{
+	__asm__ volatile("msr spsr_c, %0" : : "r" (spsr) : "memory");
+}
+
+static inline void __setSpsr(u32 spsr)
+{
+	__asm__ volatile("msr spsr_cxsf, %0" : : "r" (spsr) : "memory");
+}
+
+#endif // if !__ASSEMBLER__
diff --git a/include/arm11/debug.h b/include/arm11/debug.h
index 96ba5ee..f5c7f70 100644
--- a/include/arm11/debug.h
+++ b/include/arm11/debug.h
@@ -30,23 +30,23 @@
 // Exception tests
 /*static inline regTest(void)
 {
-	__asm__ __volatile__("mov r0, #1\n\tmov r1, #2\n\tmov r2, #3\n\tmov r3, #4\n\tmov r4, #5\n\t"
-	                     "mov r5, #6\n\tmov r6, #7\n\tmov r7, #8\n\tmov r8, #9\n\tmov r9, #10\n\t"
-	                     "mov r10, #11\n\tmov r11, #12\n\tmov r12, #13\n\tmov r13, #14\n\t"
-	                     "mov r14, #15\n\tmov r15, #16\n\t" : :);
+	__asm__ volatile("mov r0, #1\n\tmov r1, #2\n\tmov r2, #3\n\tmov r3, #4\n\tmov r4, #5\n\t"
+	                 "mov r5, #6\n\tmov r6, #7\n\tmov r7, #8\n\tmov r8, #9\n\tmov r9, #10\n\t"
+	                 "mov r10, #11\n\tmov r11, #12\n\tmov r12, #13\n\tmov r13, #14\n\t"
+	                 "mov r14, #15\n\tmov r15, #16\n\t" : :);
 }
 
 static inline breakpointTest(void)
 {
-	__asm__ __volatile__("bkpt #0xCAFE" : :);
+	__asm__ volatile("bkpt #0xCAFE" : :);
 }
 
 static inline dataAbortTest(void)
 {
-	__asm__ __volatile__("mov r0, #4\n\tmov r1, #0xEF\n\tstr r1, [r0]" : :);
+	__asm__ volatile("mov r0, #4\n\tmov r1, #0xEF\n\tstr r1, [r0]" : :);
 }
 
 static inline undefInstrTest(void)
 {
-	__asm__ __volatile__(".word 0xFFFFFFFF" : :);
+	__asm__ volatile(".word 0xFFFFFFFF" : :);
 }*/
diff --git a/include/arm11/event.h b/include/arm11/event.h
deleted file mode 100644
index 19b40f2..0000000
--- a/include/arm11/event.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#pragma once
-
-/*
- *   This file is part of fastboot 3DS
- *   Copyright (C) 2017 derrek, profi200
- *
- *   This program is free software: you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation, either version 3 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-
-
-static inline void __wfe(void)
-{
-	__asm__ __volatile__("wfe" : : : "memory");
-}
-
-static inline void __sev(void)
-{
-	__asm__ __volatile__("sev" : : : "memory");
-}
\ No newline at end of file
diff --git a/include/arm11/hardware/interrupt.h b/include/arm11/hardware/interrupt.h
index 78dd961..4373ac4 100644
--- a/include/arm11/hardware/interrupt.h
+++ b/include/arm11/hardware/interrupt.h
@@ -18,6 +18,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "arm.h"
 #include "types.h"
 
 
@@ -125,22 +126,14 @@
 void IRQ_softwareInterrupt(Interrupt id, u8 cpuMask);
 
 
-static inline void __wfi(void)
-{
-	__asm__ __volatile__("wfi" : : : "memory");
-}
-
 static inline u32 enterCriticalSection(void)
 {
-	u32 tmp;
-	__asm__("mrs %0, cpsr" : "=r" (tmp) : );
-	__asm__ __volatile__("cpsid i" : : : "memory");
-	return tmp & 0x80;
+	const u32 tmp = __getCpsr();
+	__cpsid(i);
+	return tmp & PSR_I;
 }
 
 static inline void leaveCriticalSection(u32 oldState)
 {
-	u32 tmp;
-	__asm__ __volatile__("mrs %0, cpsr" : "=r" (tmp) : );
-	__asm__ __volatile__("msr cpsr_c, %0" : : "r" ((tmp & ~0x80u) | oldState) : "memory");
+	__setCpsr_c((__getCpsr() & ~PSR_I) | oldState);
 }
diff --git a/include/arm11/spinlock.h b/include/arm11/spinlock.h
index 3c52109..e430a27 100644
--- a/include/arm11/spinlock.h
+++ b/include/arm11/spinlock.h
@@ -25,21 +25,21 @@
 static inline void spinlockLock(u32 *lock)
 {
 	u32 tmp;
-	__asm__ __volatile__("1: ldrex %0, [%1]\n"
-	                     "   teq %0, #0\n"
-	                     "   wfene\n"
-	                     "   strexeq %0, %2, [%1]\n"
-	                     "   teqeq %0, #0\n"
-	                     "   bne 1b\n"
-	                     "   mcr p15, 0, %0, c7, c10, 5" // DMB
-	                     : "=&r" (tmp) : "r" (lock), "r" (1) : "cc", "memory");
+	__asm__ volatile("1: ldrex %0, [%1]\n"
+	                 "   teq %0, #0\n"
+	                 "   wfene\n"
+	                 "   strexeq %0, %2, [%1]\n"
+	                 "   teqeq %0, #0\n"
+	                 "   bne 1b\n"
+	                 "   mcr p15, 0, %0, c7, c10, 5" // DMB
+	                 : "=&r" (tmp) : "r" (lock), "r" (1) : "cc", "memory");
 }
 
 static inline void spinlockUnlock(u32 *lock)
 {
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5\n" // DMB
-	                     "str %0, [%1]\n"
-	                     "mcr p15, 0, %0, c7, c10, 4\n" // DSB
-	                     "sev"
-	                     : : "r" (0), "r" (lock) : "memory");
+	__asm__ volatile("mcr p15, 0, %0, c7, c10, 5\n" // DMB
+	                 "str %0, [%1]\n"
+	                 "mcr p15, 0, %0, c7, c10, 4\n" // DSB
+	                 "sev"
+	                 : : "r" (0), "r" (lock) : "memory");
 }
diff --git a/include/arm11/start.h b/include/arm11/start.h
index 064228b..53fab51 100644
--- a/include/arm11/start.h
+++ b/include/arm11/start.h
@@ -24,10 +24,3 @@
 
 void clearMem(u32 *adr, u32 size);
 void deinitCpu(void);
-
-static inline u32 getCpuId(void)
-{
-	u32 cpuId;
-	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 5" : "=r" (cpuId) : );
-	return cpuId & 3;
-}
diff --git a/include/arm9/hardware/interrupt.h b/include/arm9/hardware/interrupt.h
index e0770e1..aa5fb43 100644
--- a/include/arm9/hardware/interrupt.h
+++ b/include/arm9/hardware/interrupt.h
@@ -18,6 +18,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "arm.h"
 #include "types.h"
 
 
@@ -83,22 +84,14 @@
 void IRQ_unregisterHandler(Interrupt id);
 
 
-static inline void __wfi(void)
-{
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c0, 4" : : "r" (0) : "memory");
-}
-
 static inline u32 enterCriticalSection(void)
 {
 	u32 tmp;
-	__asm__ __volatile__("mrs %0, cpsr" : "=r" (tmp) : );
-	__asm__ __volatile__("msr cpsr_c, %0" : : "r" (tmp | 0x80) : "memory");
-	return tmp & 0x80;
+	__setCpsr_c((tmp = __getCpsr()) | PSR_I);
+	return tmp & PSR_I;
 }
 
 static inline void leaveCriticalSection(u32 oldState)
 {
-	u32 tmp;
-	__asm__ __volatile__("mrs %0, cpsr" : "=r" (tmp) : );
-	__asm__ __volatile__("msr cpsr_c, %0" : : "r" ((tmp & ~0x80u) | oldState) : "memory");
+	__setCpsr_c((__getCpsr() & ~PSR_I) | oldState);
 }
diff --git a/source/arm11/debug.c b/source/arm11/debug.c
index 858c20b..bae56d9 100644
--- a/source/arm11/debug.c
+++ b/source/arm11/debug.c
@@ -27,6 +27,7 @@
 #include "ipc_handler.h"
 #include "hardware/gfx.h"
 #include "arm11/hardware/interrupt.h"
+#include "arm.h"
 #include "arm11/hardware/mcu.h"
 #include "arm11/hardware/hid.h"
 
diff --git a/source/arm11/firm.c b/source/arm11/firm.c
index a04a939..19f8f96 100644
--- a/source/arm11/firm.c
+++ b/source/arm11/firm.c
@@ -70,7 +70,7 @@
 	deinitCpu();
 
 	// Change sp to a safe location
-	__asm__ __volatile__("mov sp, %0" : : "r" (A11_STUB_ENTRY) : "sp");
+	__asm__ volatile("mov sp, %0" : : "r" (A11_STUB_ENTRY) : "sp");
 	((void (*)(void))A11_STUB_ENTRY)();
 	while(1);
 }
diff --git a/source/arm11/hardware/exception.s b/source/arm11/hardware/exception.s
index 50a9652..645eb98 100644
--- a/source/arm11/hardware/exception.s
+++ b/source/arm11/hardware/exception.s
@@ -16,7 +16,9 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "arm.h"
 #include "asmfunc.h"
+#include "mem_map.h"
 
 .arm
 .cpu mpcore
@@ -29,21 +31,21 @@
 
 
 ASM_FUNC undefInstrHandler
-	msr cpsr_f, #(0<<29)           @ Abuse conditional flags in cpsr for temporary exception type storage
+	msr cpsr_f, #0<<29             @ Abuse conditional flags in cpsr for temporary exception type storage
 	b exceptionHandler
 ASM_FUNC prefetchAbortHandler
-	msr cpsr_f, #(1<<29)
+	msr cpsr_f, #1<<29
 	b exceptionHandler
 ASM_FUNC dataAbortHandler
-	msr cpsr_f, #(2<<29)
+	msr cpsr_f, #2<<29
 ASM_FUNC exceptionHandler
 	sub sp, #68
 	stmia sp, {r0-r14}^            @ Save all user/system mode regs except pc
 	mrs r2, spsr                   @ Get saved cpsr
 	mrs r3, cpsr
 	lsr r0, r3, #29                @ Get back the exception type from cpsr
-	and r1, r2, #0x1F
-	cmp r1, #0x10                  @ User mode
+	and r1, r2, #PSR_MODE_MASK
+	cmp r1, #PSR_USER_MODE
 	beq exceptionHandler_skip_other_mode
 	add r4, sp, #32
 	msr cpsr_c, r2
@@ -63,10 +65,10 @@
 
 ASM_FUNC irqHandler
 	sub lr, lr, #4
-	srsfd sp!, #31               @ Store lr and spsr on system mode stack
-	cps #31                      @ Switch to system mode
+	srsfd sp!, #PSR_SYS_MODE     @ Store lr and spsr on system mode stack
+	cps #PSR_SYS_MODE
 	stmfd sp!, {r0-r3, r12, lr}
-	ldr r12, =0x17E00000
+	ldr r12, =MPCORE_PRIV_REG_BASE
 	ldr r0, [r12, #0x10C]        @ REG_CPU_II_AKN
 	and r1, r0, #0x7F
 	cmp r1, #32
@@ -82,7 +84,7 @@
 	str r0, [sp, #-4]!           @ A single ldr/str can't be interrupted
 	blx r3
 	ldr r0, [sp], #4
-	ldr r12, =0x17E00000
+	ldr r12, =MPCORE_PRIV_REG_BASE
 	cpsid i
 irqHandler_skip_processing:
 	str r0, [r12, #0x110]        @ REG_CPU_II_EOI
diff --git a/source/arm11/hardware/gfx.c b/source/arm11/hardware/gfx.c
index 1cae2c6..b46d3a8 100644
--- a/source/arm11/hardware/gfx.c
+++ b/source/arm11/hardware/gfx.c
@@ -28,7 +28,7 @@
 #include "hardware/gfx.h"
 #include "arm11/hardware/mcu.h"
 #include "arm11/hardware/interrupt.h"
-#include "arm11/event.h"
+#include "arm.h"
 
 
 #define PDN_REGS_BASE           (IO_MEM_ARM9_ARM11 + 0x40000)
diff --git a/source/arm11/hardware/interrupt.c b/source/arm11/hardware/interrupt.c
index f3d2a03..22638db 100644
--- a/source/arm11/hardware/interrupt.c
+++ b/source/arm11/hardware/interrupt.c
@@ -20,6 +20,7 @@
 #include "mem_map.h"
 #include "arm11/hardware/interrupt.h"
 #include "arm11/start.h"
+#include "arm.h"
 
 
 #define REG_CFG11_FIQ_CNT    *((vu8* )(IO_MEM_ARM9_ARM11 + 0x40000 + 0x0104))
@@ -67,7 +68,7 @@
 	REG_CPU_II_CNT = 0;
 
 
-	if(!getCpuId())
+	if(!__getCpuId())
 	{
 		// Disable FIQs
 		REG_CFG11_FIQ_CNT = 1;
@@ -130,7 +131,7 @@
 
 void IRQ_registerHandler(Interrupt id, u8 prio, u8 cpuMask, bool edgeTriggered, IrqHandler handler)
 {
-	const u32 cpuId = getCpuId();
+	const u32 cpuId = __getCpuId();
 	if(!cpuMask) cpuMask = 1u<<cpuId;
 
 	const u32 oldState = enterCriticalSection();
@@ -160,7 +161,7 @@
 
 	REGs_GID_ENA_CLR[id>>5] = 1u<<(id % 32);
 
-	irqHandlerTable[(id < 32 ? 32 * getCpuId() + id : 96u + id)] = (IrqHandler)NULL;
+	irqHandlerTable[(id < 32 ? 32 * __getCpuId() + id : 96u + id)] = (IrqHandler)NULL;
 
 	leaveCriticalSection(oldState);
 }
diff --git a/source/arm11/hardware/mmu.c b/source/arm11/hardware/mmu.c
index 45210c4..9a3c61e 100644
--- a/source/arm11/hardware/mmu.c
+++ b/source/arm11/hardware/mmu.c
@@ -19,7 +19,7 @@
 #include "types.h"
 #include "mem_map.h"
 #include "arm11/start.h"
-#include "arm11/event.h"
+#include "arm.h"
 
 
 #define SCU_REGS_BASE      (MPCORE_PRIV_REG_BASE)
@@ -108,17 +108,17 @@
 void setupMmu(void)
 {
 	// TTBR0 address shared page table walk and outer cachable write-through, no allocate on write
-	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 0" : : "r" (A11_MMU_TABLES_BASE | 0x12u));
+	__setTtbr0(A11_MMU_TABLES_BASE | 0x12);
 	// Use the 16 KB L1 table only
-	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 2" : : "r" (0u));
+	__setTtbcr(0);
 	// Domain 1 = client, remaining domains all = no access
-	__asm__ __volatile__("mcr p15, 0, %0, c3, c0, 0" : : "r" (4u));
+	__setDacr(4);
 	// Context ID Register (ASID = 0, PROCID = 0)
-	__asm__ __volatile__("mcr p15, 0, %0, c13, c0, 1" : : "r" (0u));
+	__setCidr(0);
 
 
 	static volatile bool syncFlag = false;
-	if(!getCpuId())
+	if(!__getCpuId())
 	{
 		// Clear L1 and L2 tables
 		clearMem((u32*)A11_MMU_TABLES_BASE, 0x4C00u);
@@ -174,28 +174,23 @@
 	else while(!syncFlag) __wfe();
 
 
-	// Invalidate TLB (Unified TLB operation) + Data Synchronization Barrier
-	__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0\n"
-	                     "mcr p15, 0, %0, c7, c10, 4" : : "r" (0u));
+	// Invalidate TLB (Unified TLB operation)
+	__asm__ volatile("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
+	__dsb();
 
 
-	u32 tmp;
-	// Modify Auxiliary Control Register
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r" (tmp) : );
-	tmp |= 0x6Fu;     // Enable Return stack, Dynamic branch prediction, Static branch prediction,
-	                  // Instruction folding, SMP mode: the CPU is taking part in coherency
-	                  // and L1 parity checking
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r" (tmp));
+	// Enable Return stack, Dynamic branch prediction, Static branch prediction,
+	// Instruction folding, SMP mode: the CPU is taking part in coherency
+	// and L1 parity checking
+	__setAcr(__getAcr() | 0x6F);
 
-	// Modify Control Register
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0" : "=r" (tmp) : );
-	tmp |= 0xC03805u; // Enable MMU, D-Cache, Program flow prediction,
-	                  // I-Cache, high exception vectors, Unaligned data access,
-	                  // subpage AP bits disabled
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0" : : "r" (tmp));
+	// Enable MMU, D-Cache, Program flow prediction,
+	// I-Cache, high exception vectors, Unaligned data access,
+	// subpage AP bits disabled
+	__setCr(__getCr() | 0xC03805);
 
-	// Invalidate all caches + Data Synchronization Barrier
-	__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0\n"
-	                     "mcr p15, 0, %0, c7, c10, 4\n" // DSB
-	                     "mcr p15, 0, %0, c7, c5, 4" : : "r" (0u));
+	// Invalidate Both Caches. Also flushes the branch target cache
+	__asm__ volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (0) : "memory");
+	__dsb();
+	__isb();
 }
diff --git a/source/arm11/hardware/timer.c b/source/arm11/hardware/timer.c
index a31e69b..37a2343 100644
--- a/source/arm11/hardware/timer.c
+++ b/source/arm11/hardware/timer.c
@@ -21,7 +21,7 @@
 #include "arm11/hardware/timer.h"
 #include "arm11/hardware/interrupt.h"
 #include "fb_assert.h"
-#include "arm11/event.h"
+#include "arm.h"
 
 
 #define TIMER_REGS_BASE     (MPCORE_PRIV_REG_BASE + 0x600)
diff --git a/source/arm11/menu/menu_util.c b/source/arm11/menu/menu_util.c
index 8fdad94..3081d6b 100644
--- a/source/arm11/menu/menu_util.c
+++ b/source/arm11/menu/menu_util.c
@@ -22,7 +22,7 @@
 #include "hardware/gfx.h"
 #include "arm11/hardware/hid.h"
 #include "arm11/hardware/mcu.h"
-#include "arm11/hardware/interrupt.h"
+#include "arm.h"
 #include "arm11/menu/menu_color.h"
 #include "arm11/menu/menu_util.h"
 #include "arm11/console.h"
diff --git a/source/arm11/power.c b/source/arm11/power.c
index 6e58242..6f709bf 100644
--- a/source/arm11/power.c
+++ b/source/arm11/power.c
@@ -25,6 +25,7 @@
 #include "hardware/cache.h"
 #include "hardware/gfx.h"
 #include "hardware/pxi.h"
+#include "arm.h"
 
 
 
@@ -37,7 +38,7 @@
 	TIMER_sleepMs(400);
 
 	flushDCache();
-	__asm__ __volatile__("cpsid aif" : : : "memory");
+	__cpsid(aif);
 }
 
 noreturn void power_off(void)
diff --git a/source/arm11/start.s b/source/arm11/start.s
index 304e310..b918581 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -16,6 +16,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "arm.h"
 #include "mem_map.h"
 
 .arm
@@ -74,7 +75,7 @@
 
 
 _start:
-	cpsid aif, #19             @ Disable all interrupts, SVC mode
+	cpsid aif, #PSR_SVC_MODE
 
 	@ Control register:
 	@ [29] Force AP functionality             : disabled
@@ -105,15 +106,16 @@
 	bleq stubExceptionVectors   @ Stub the vectors in AXIWRAM bootrom vectors jump to
 
 	mov sp, #0                  @ unused SVC mode sp
-	cps #23                     @ Abort mode
-	ldr sp, =A11_EXC_STACK_END
-	cps #27                     @ Undefined mode
-	ldr sp, =A11_EXC_STACK_END
-	cps #17                     @ FIQ mode
+	cps #PSR_FIQ_MODE
 	mov sp, #0                  @ Unused
-	cps #18                     @ IRQ mode
+	cps #PSR_IRQ_MODE
 	mov sp, #0                  @ not needed
-	cps #31                     @ System mode
+	cps #PSR_ABORT_MODE
+	ldr r0, =A11_EXC_STACK_END
+	mov sp, r0
+	cps #PSR_UNDEF_MODE
+	mov sp, r0
+	cps #PSR_SYS_MODE
 	adr r2, _sysmode_stacks
 	ldr sp, [r2, r4, lsl #2]
 
@@ -216,7 +218,7 @@
 deinitCpu:
 	mov r3, lr
 
-	cpsid aif, #31              @ System mode
+	cpsid aif, #PSR_SYS_MODE
 	bl stubExceptionVectors
 	bl flushDCache
 	mov r2, #0
diff --git a/source/arm11/system.c b/source/arm11/system.c
index 32f45cc..6237ed3 100644
--- a/source/arm11/system.c
+++ b/source/arm11/system.c
@@ -24,6 +24,7 @@
 #include "arm11/hardware/i2c.h"
 #include "arm11/hardware/mcu.h"
 #include "arm11/hardware/hid.h"
+#include "arm.h"
 
 
 
@@ -37,7 +38,7 @@
 	IRQ_init();
 	TIMER_init();
 
-	if(!getCpuId())
+	if(!__getCpuId())
 	{
 		I2C_init();
 		hidInit();
@@ -52,5 +53,5 @@
 		((void (*)(void))0x0001004C)();
 	}
 
-	__asm__ __volatile__("cpsie i" : : : "memory"); // Enables interrupts
+	__cpsie(i); // Enables interrupts
 }
diff --git a/source/arm9/hardware/crypto.c b/source/arm9/hardware/crypto.c
index cdacd77..4f63c0e 100644
--- a/source/arm9/hardware/crypto.c
+++ b/source/arm9/hardware/crypto.c
@@ -23,6 +23,7 @@
 #include "arm9/hardware/crypto.h"
 #include "arm9/hardware/interrupt.h"
 #include "arm9/hardware/ndma.h"
+#include "arm.h"
 
 
 
diff --git a/source/arm9/hardware/exception.s b/source/arm9/hardware/exception.s
index 02f9dda..fe74bf0 100644
--- a/source/arm9/hardware/exception.s
+++ b/source/arm9/hardware/exception.s
@@ -16,6 +16,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "arm.h"
 #include "asmfunc.h"
 #include "mem_map.h"
 
@@ -30,21 +31,21 @@
 
 
 ASM_FUNC undefInstrHandler
-	msr cpsr_f, #(0<<29)           @ Abuse conditional flags in cpsr for temporary exception type storage
+	msr cpsr_f, #0<<29             @ Abuse conditional flags in cpsr for temporary exception type storage
 	b exceptionHandler
 ASM_FUNC prefetchAbortHandler
-	msr cpsr_f, #(1<<29)
+	msr cpsr_f, #1<<29
 	b exceptionHandler
 ASM_FUNC dataAbortHandler
-	msr cpsr_f, #(2<<29)
+	msr cpsr_f, #2<<29
 ASM_FUNC exceptionHandler
 	sub sp, #68
 	stmia sp, {r0-r14}^            @ Save all user/system mode regs except pc
 	mrs r2, spsr                   @ Get saved cpsr
 	mrs r3, cpsr
 	lsr r0, r3, #29                @ Get back the exception type from cpsr
-	and r1, r2, #0x1F
-	cmp r1, #0x10                  @ User mode
+	and r1, r2, #PSR_MODE_MASK
+	cmp r1, #PSR_USER_MODE
 	beq exceptionHandler_skip_other_mode
 	add r4, sp, #32
 	msr cpsr_c, r2
@@ -65,7 +66,7 @@
 ASM_FUNC irqHandler
 	sub lr, lr, #4
 	stmfd sp!, {r0-r3, r12, lr}
-	ldr r12, =0x10001000             @ REG_IRQ_IE
+	ldr r12, =IO_MEM_ARM9_ONLY + 0x1000 @ REG_IRQ_IE
 	ldrd r0, r1, [r12]
 	and r1, r0, r1
 	mov r3, #0x80000000
@@ -82,11 +83,11 @@
 	beq irqHandler_skip_processing
 	mrs r3, spsr
 	str r3, [sp, #-4]!
-	msr cpsr_c, #0x5F                @ System mode, IRQ enabled
+	msr cpsr_c, #PSR_F | PSR_SYS_MODE
 	str lr, [sp, #-4]!               @ A single ldr/str can't be interrupted
 	blx r2
 	ldr lr, [sp], #4
-	msr cpsr_c, #0xD2                @ IRQ mode, IRQ disabled
+	msr cpsr_c, #PSR_INT_OFF | PSR_IRQ_MODE
 	ldr r0, [sp], #4
 	msr spsr_cxsf, r0
 irqHandler_skip_processing:
diff --git a/source/arm9/hardware/ndma.c b/source/arm9/hardware/ndma.c
index 9118747..3dd81da 100644
--- a/source/arm9/hardware/ndma.c
+++ b/source/arm9/hardware/ndma.c
@@ -20,6 +20,7 @@
 #include "fb_assert.h"
 #include "arm9/hardware/ndma.h"
 #include "arm9/hardware/interrupt.h"
+#include "arm.h"
 
 
 
diff --git a/source/arm9/hardware/timer.c b/source/arm9/hardware/timer.c
index 2f140fd..1c9991c 100644
--- a/source/arm9/hardware/timer.c
+++ b/source/arm9/hardware/timer.c
@@ -20,6 +20,7 @@
 #include "types.h"
 #include "arm9/hardware/timer.h"
 #include "arm9/hardware/interrupt.h"
+#include "arm.h"
 
 
 #define TIMER_REGS_BASE   (IO_MEM_ARM9_ONLY + 0x3000)
diff --git a/source/arm9/main.c b/source/arm9/main.c
index 5885cff..8e76da6 100644
--- a/source/arm9/main.c
+++ b/source/arm9/main.c
@@ -19,7 +19,7 @@
 #include "types.h"
 #include "mem_map.h"
 #include "arm9/debug.h"
-#include "arm9/hardware/interrupt.h"
+#include "arm.h"
 #include "arm9/firm.h"
 
 
diff --git a/source/arm9/start.s b/source/arm9/start.s
index e89e0db..6ae93f2 100644
--- a/source/arm9/start.s
+++ b/source/arm9/start.s
@@ -16,6 +16,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "arm.h"
 #include "mem_map.h"
 
 .arm
@@ -57,7 +58,7 @@
 	.word   (VERS_MAJOR<<16 | VERS_MINOR)
 
 _start:
-	msr cpsr_cxsf, #0xD3         @ Disable all interrupts, SVC mode
+	msr cpsr_cxsf, #PSR_INT_OFF | PSR_SVC_MODE
 
 	@ Control register:
 	@ [19] ITCM load mode         : disabled
@@ -82,13 +83,13 @@
 	bl setupTcms                @ Setup and enable DTCM and ITCM
 
 	mov sp, #0                  @ unused SVC mode sp
-	msr cpsr_cxsf, #0xD7        @ Abort mode
-	mov sp, #A9_EXC_STACK_END
-	msr cpsr_cxsf, #0xDB        @ Undefined mode
-	mov sp, #A9_EXC_STACK_END
-	msr cpsr_cxsf, #0xD2        @ IRQ mode
+	msr cpsr_cxsf, #PSR_INT_OFF | PSR_IRQ_MODE
 	ldr sp, =A9_IRQ_STACK_END
-	msr cpsr_cxsf, #0xDF        @ System mode
+	msr cpsr_cxsf, #PSR_INT_OFF | PSR_ABORT_MODE
+	mov sp, #A9_EXC_STACK_END
+	msr cpsr_cxsf, #PSR_INT_OFF | PSR_UNDEF_MODE
+	mov sp, #A9_EXC_STACK_END
+	msr cpsr_cxsf, #PSR_INT_OFF | PSR_SYS_MODE
 	ldr sp, =A9_STACK_END
 
 	bl setupMpu
@@ -283,7 +284,7 @@
 deinitCpu:
 	mov r3, lr
 
-	msr cpsr_cxsf, #0xDF        @ System mode
+	msr cpsr_cxsf, #PSR_INT_OFF | PSR_SYS_MODE
 	@ Stub vectors to endless loops
 	mov r0, #A9_RAM_BASE
 	mov r1, #6
diff --git a/source/fb_assert.c b/source/fb_assert.c
index 392878f..e6c57f8 100644
--- a/source/fb_assert.c
+++ b/source/fb_assert.c
@@ -27,6 +27,7 @@
 	#include "arm11/hardware/interrupt.h"
 #endif
 #include "hardware/gfx.h"
+#include "arm.h"