diff --git a/include/arm9/ndma.h b/include/arm9/ndma.h
index d3e1d6d..890ab76 100644
--- a/include/arm9/ndma.h
+++ b/include/arm9/ndma.h
@@ -1,5 +1,5 @@
 /**
- * 2016
+ * 2017
  * profi200
  */
 
@@ -140,6 +140,15 @@
 void NDMA_init(void);
 
 /**
+ * @brief      Asynchronous copying of data using the NDMA engine.
+ *
+ * @param      dest    Pointer to destination memory. Must be 4 bytes aligned.
+ * @param      source  Pointer to source data. Must be 4 bytes aligned.
+ * @param[in]  num     The size of the data. Must be a multiple of 4.
+ */
+void NDMA_copyAsync(u32 *dest, const u32 *source, u32 num);
+
+/**
  * @brief      Copies data using the NDMA engine.
  *
  * @param      dest    Pointer to destination memory. Must be 4 bytes aligned.
@@ -149,6 +158,15 @@
 void NDMA_copy(u32 *dest, const u32 *source, u32 num);
 
 /**
+ * @brief      Asynchronous memory fill with the given value using the NDMA engine.
+ *
+ * @param      dest   Pointer to destination memory. Must be 4 bytes aligned.
+ * @param[in]  value  The value each 32-bit word will be set to.
+ * @param[in]  num    The size of the memory to fill. Must be a multiple of 4.
+ */
+void NDMA_fillAsync(u32 *dest, u32 value, u32 num);
+
+/**
  * @brief      Fills memory with the given value using the NDMA engine.
  *
  * @param      dest   Pointer to destination memory. Must be 4 bytes aligned.
diff --git a/source/arm9/ndma.c b/source/arm9/ndma.c
index 059f468..1606864 100644
--- a/source/arm9/ndma.c
+++ b/source/arm9/ndma.c
@@ -1,5 +1,5 @@
 /**
- * 2016
+ * 2017
  * profi200
  */
 
@@ -27,7 +27,7 @@
 	leaveCriticalSection(oldState);
 }
 
-void NDMA_copy(u32 *dest, const u32 *source, u32 num)
+void NDMA_copyAsync(u32 *dest, const u32 *source, u32 num)
 {
 	assert(((u32)dest >= ITCM_BOOT9_MIRROR + ITCM_SIZE) && (((u32)dest < DTCM_BASE) || ((u32)dest >= DTCM_BASE + DTCM_SIZE)));
 	assert(((u32)source >= ITCM_BOOT9_MIRROR + ITCM_SIZE) && (((u32)source < DTCM_BASE) || ((u32)source >= DTCM_BASE + DTCM_SIZE)));
@@ -37,6 +37,27 @@
 	REG_NDMA7_WRITE_CNT = num;
 	REG_NDMA7_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
 	REG_NDMA7_CNT = NDMA_ENABLE | NDMA_IRQ_ENABLE | NDMA_STARTUP_IMMEDIATE | NDMA_SRC_UPDATE_INC | NDMA_DST_UPDATE_INC;
+}
+
+void NDMA_copy(u32 *dest, const u32 *source, u32 num)
+{
+	NDMA_copyAsync(dest, source, num);
+
+	while(REG_NDMA7_CNT & NDMA_ENABLE)
+	{
+		waitForIrq();
+	}
+}
+
+void NDMA_fillAsync(u32 *dest, u32 value, u32 num)
+{
+	assert(((u32)dest >= ITCM_BOOT9_MIRROR + ITCM_SIZE) && (((u32)dest < DTCM_BASE) || ((u32)dest >= DTCM_BASE + DTCM_SIZE)));
+
+	REG_NDMA7_DST_ADDR = (u32)dest;
+	REG_NDMA7_WRITE_CNT = num;
+	REG_NDMA7_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
+	REG_NDMA7_FILL_DATA = value;
+	REG_NDMA7_CNT = NDMA_ENABLE | NDMA_IRQ_ENABLE | NDMA_STARTUP_IMMEDIATE | NDMA_SRC_UPDATE_FILL | NDMA_DST_UPDATE_INC;
 
 	while(REG_NDMA7_CNT & NDMA_ENABLE)
 	{
@@ -46,13 +67,7 @@
 
 void NDMA_fill(u32 *dest, u32 value, u32 num)
 {
-	assert(((u32)dest >= ITCM_BOOT9_MIRROR + ITCM_SIZE) && (((u32)dest < DTCM_BASE) || ((u32)dest >= DTCM_BASE + DTCM_SIZE)));
-
-	REG_NDMA7_DST_ADDR = (u32)dest;
-	REG_NDMA7_WRITE_CNT = num;
-	REG_NDMA7_BLOCK_CNT = NDMA_BLOCK_SYS_FREQ;
-	REG_NDMA7_FILL_DATA = value;
-	REG_NDMA7_CNT = NDMA_ENABLE | NDMA_IRQ_ENABLE | NDMA_STARTUP_IMMEDIATE | NDMA_SRC_UPDATE_FILL | NDMA_DST_UPDATE_INC;
+	NDMA_fillAsync(dest, value, num);
 
 	while(REG_NDMA7_CNT & NDMA_ENABLE)
 	{