diff --git a/arm11/Makefile b/arm11/Makefile index e1308a4..3618de3 100644 --- a/arm11/Makefile +++ b/arm11/Makefile @@ -35,13 +35,13 @@ #--------------------------------------------------------------------------------- ARCH := -march=armv6k -mtune=mpcore -mfloat-abi=hard -mtp=soft -marm -mthumb-interwork -CFLAGS := $(ARCH) -std=c11 -O2 -g -flto -fstrict-aliasing -mword-relocations -fomit-frame-pointer \ - -ffast-math -ffunction-sections -Wall -Wextra -Wno-unused-function +CFLAGS := $(ARCH) -std=c11 -O2 -g -flto -mword-relocations -ffunction-sections \ + -Wall -Wextra -Wno-unused-function CFLAGS += $(INCLUDE) $(DEFINES) -CXXFLAGS := $(ARCH) -std=c11 -O2 -g -flto -fno-rtti -fno-exceptions -fstrict-aliasing \ - -mword-relocations -fomit-frame-pointer -ffast-math -ffunction-sections -Wall -Wextra \ +CXXFLAGS := $(ARCH) -std=c++14 -O2 -g -flto -fno-rtti -fno-exceptions \ + -mword-relocations -ffunction-sections -Wall -Wextra \ -Wno-unused-function CXXFLAGS += $(INCLUDE) $(DEFINES) diff --git a/arm9/Makefile b/arm9/Makefile index 8cabf4d..f202795 100644 --- a/arm9/Makefile +++ b/arm9/Makefile @@ -34,13 +34,14 @@ #--------------------------------------------------------------------------------- ARCH := -march=armv5te -mtune=arm946e-s -mfloat-abi=soft -mtp=soft -marm -mthumb-interwork -CFLAGS := $(ARCH) -std=c11 -O2 -g -flto -fstrict-aliasing -mword-relocations -fomit-frame-pointer \ - -ffast-math -ffunction-sections -Wall -Wextra +CFLAGS := $(ARCH) -std=c11 -O2 -g -flto -mword-relocations -ffunction-sections \ + -Wall -Wextra -Wno-unused-function CFLAGS += $(INCLUDE) $(DEFINES) -CXXFLAGS := $(ARCH) -std=c11 -O2 -g -flto -fno-rtti -fno-exceptions -fstrict-aliasing \ - -mword-relocations -fomit-frame-pointer -ffast-math -ffunction-sections -Wall -Wextra +CXXFLAGS := $(ARCH) -std=c++14 -O2 -g -flto -fno-rtti -fno-exceptions \ + -mword-relocations -ffunction-sections -Wall -Wextra \ + -Wno-unused-function CXXFLAGS += $(INCLUDE) $(DEFINES) diff --git a/include/arm11/hardware/i2c.h b/include/arm11/hardware/i2c.h index dd7472a..a9c298b 100644 --- a/include/arm11/hardware/i2c.h +++ b/include/arm11/hardware/i2c.h @@ -30,8 +30,6 @@ #define I2C_IRQ_ENABLE (1u<<6) #define I2C_ENABLE (1u<<7) -#define I2C_GET_ACK(reg) ((bool)((reg)>>4 & 1u)) - typedef enum { @@ -99,32 +97,3 @@ * @return Returns true on success and false on failure. */ bool I2C_writeReg(I2cDevice devId, u8 regAddr, u8 data); - - -static inline u8 i2cmcu_readreg_hid_irq(void) -{ - u8 data; - if(!I2C_readRegBuf(I2C_DEV_MCU, 0x10, &data, 1)) return 0; - return data; -} - -static inline u8 i2cmcu_readreg_hid_held(void) -{ - u8 data[19]; - if(!I2C_readRegBuf(I2C_DEV_MCU, 0x7F, data, sizeof(data))) return 0; - return data[18]; -} - -static inline bool i2cmcu_lcd_backlight_poweron(void) -{ - return I2C_writeReg(I2C_DEV_MCU, 0x22, 1<<5 | 1<<3); // bit3 = lower screen, bit5 = upper -} - - -#define MCU_HID_POWER_BUTTON_PRESSED (1u) -#define MCU_HID_POWER_BUTTON_LONG_PRESSED (1u<<1) -#define MCU_HID_HOME_BUTTON_PRESSED (1u<<2) -#define MCU_HID_HOME_BUTTON_RELEASED (1u<<3) -#define MCU_HID_HOME_BUTTON_NOT_HELD (1u<<1) -#define MCU_HID_SHELL_GOT_CLOSED (1u<<5) -#define MCU_HID_SHELL_GOT_OPENED (1u<<6) diff --git a/include/arm11/hardware/interrupt.h b/include/arm11/hardware/interrupt.h index 4569ba3..594771e 100644 --- a/include/arm11/hardware/interrupt.h +++ b/include/arm11/hardware/interrupt.h @@ -85,7 +85,10 @@ IRQ_PXI_UNK = 81, // Unknown what this is for IRQ_PXI_NOT_FULL = 82, IRQ_PXI_NOT_EMPTY = 83, + IRQ_I2C1 = 84, + IRQ_I2C2 = 85, IRQ_PDN = 88, + IRQ_I2C3 = 92, IRQ_SHELL_OPENED = 96, IRQ_SHELL_CLOSED = 98, IRQ_TOUCHSCREEN = 99, // Triggers on hitting the touchscreen. diff --git a/include/arm11/hardware/mcu.h b/include/arm11/hardware/mcu.h index d4dde5b..53bdbd7 100644 --- a/include/arm11/hardware/mcu.h +++ b/include/arm11/hardware/mcu.h @@ -21,6 +21,15 @@ #include "types.h" +#define MCU_HID_POWER_BUTTON_PRESSED (1u) +#define MCU_HID_POWER_BUTTON_LONG_PRESSED (1u<<1) +#define MCU_HID_HOME_BUTTON_PRESSED (1u<<2) +#define MCU_HID_HOME_BUTTON_RELEASED (1u<<3) +#define MCU_HID_HOME_BUTTON_NOT_HELD (1u<<1) +#define MCU_HID_SHELL_GOT_CLOSED (1u<<5) +#define MCU_HID_SHELL_GOT_OPENED (1u<<6) + + void MCU_init(void); void MCU_disableLEDs(void); @@ -32,3 +41,6 @@ bool MCU_readBatteryChargeState(void); u8 MCU_readSystemModel(void); void MCU_readRTC(void *rtc); +u8 MCU_readReceivedIrqs(void); +u8 MCU_readHidHeld(void); +bool MCU_powerOnLcdBacklights(void); diff --git a/include/arm11/hardware/timer.h b/include/arm11/hardware/timer.h index 9e5c07c..f6fa85f 100644 --- a/include/arm11/hardware/timer.h +++ b/include/arm11/hardware/timer.h @@ -21,7 +21,7 @@ #include "types.h" -#define TIMER_BASE_FREQ (268111856.0) +#define TIMER_BASE_FREQ (268111856.f) #define TIMER_ENABLE (1u) #define TIMER_SINGLE_SHOT (0u) @@ -75,5 +75,5 @@ // Sleeps ms milliseconds. ms can be up to 32000. static inline void TIMER_sleepMs(u32 ms) { - TIMER_sleepTicks(TIMER_FREQ(1, 1000.0) * ms); + TIMER_sleepTicks(TIMER_FREQ(1, 1000) * ms); } diff --git a/include/arm9/hardware/timer.h b/include/arm9/hardware/timer.h index fbb32ef..052524e 100644 --- a/include/arm9/hardware/timer.h +++ b/include/arm9/hardware/timer.h @@ -21,17 +21,17 @@ #include "types.h" -#define TIMER_BASE_FREQ (67027963.95) +#define TIMER_BASE_FREQ (67027964) #define TIMER_COUNT_UP (1u<<2) // For cascading at least 2 timers #define TIMER_IRQ_ENABLE (1u<<6) #define TIMER_ENABLE (1u<<7) // Convenience macros for calculating the ticks. Based on libnds -#define TIMER_FREQ(n) (0x10000u - (u16)(TIMER_BASE_FREQ / (n))) -#define TIMER_FREQ_64(n) (0x10000u - (u16)(TIMER_BASE_FREQ / 64.0 / (n))) -#define TIMER_FREQ_256(n) (0x10000u - (u16)(TIMER_BASE_FREQ / 256.0 / (n))) -#define TIMER_FREQ_1024(n) (0x10000u - (u16)(TIMER_BASE_FREQ / 1024.0 / (n))) +#define TIMER_FREQ(n) (-TIMER_BASE_FREQ / (n)) +#define TIMER_FREQ_64(n) (-(TIMER_BASE_FREQ / 64) / (n)) +#define TIMER_FREQ_256(n) (-(TIMER_BASE_FREQ / 256) / (n)) +#define TIMER_FREQ_1024(n) (-(TIMER_BASE_FREQ / 1024) / (n)) typedef enum diff --git a/source/arm11/hardware/hid.c b/source/arm11/hardware/hid.c index 0422fb5..1fe9b74 100644 --- a/source/arm11/hardware/hid.c +++ b/source/arm11/hardware/hid.c @@ -23,13 +23,14 @@ #include "types.h" #include "mem_map.h" #include "arm11/hardware/hid.h" -#include "arm11/hardware/i2c.h" +#include "arm11/hardware/mcu.h" #include "arm11/hardware/interrupt.h" #include "arm11/hardware/gpio.h" static u32 kHeld = 0, kDown = 0, kUp = 0; -static vu32 homeShellState = 0, powerWifiState = 0; +static u32 homeShellState = 0, powerWifiState = 0; +static volatile bool mcuIrq = false; @@ -44,12 +45,21 @@ //I2C_writeRegBuf(I2C_DEV_MCU, 0x18, (const u8*)&mcuInterruptMask, 4); IRQ_registerHandler(IRQ_MCU_HID, 14, 0, true, hidIrqHandler); - GPIO_setBit(19, 9); // This enables the MCU HID IRQ + GPIO_setBit(19, 9); // This enables the MCU IRQ. } static void hidIrqHandler(UNUSED u32 intSource) { - const u32 state = (u32)i2cmcu_readreg_hid_irq(); + mcuIrq = true; +} + +static void updateMcuIrqState(void) +{ + // TODO: We should probably disable IRQs temporarily here. + if(!mcuIrq) return; + mcuIrq = false; + + const u32 state = (u32)MCU_readReceivedIrqs(); u32 tmp = powerWifiState; tmp |= state & 3; @@ -83,13 +93,13 @@ bool hidIsHomeButtonHeldRaw(void) { - u8 buf[19]; - if(!I2C_readRegBuf(I2C_DEV_MCU, 0x7F, buf, 19)) return false; - return !(buf[18] & 1u<<1); + return !(MCU_readHidHeld() & 1u<<1); } void hidScanInput(void) { + updateMcuIrqState(); + u32 kOld = kHeld; kHeld = homeShellState | REG_HID_PAD;; kDown = (~kOld) & kHeld; diff --git a/source/arm11/hardware/i2c.c b/source/arm11/hardware/i2c.c index 156a647..ac816e5 100644 --- a/source/arm11/hardware/i2c.c +++ b/source/arm11/hardware/i2c.c @@ -23,65 +23,65 @@ #define I2C1_REGS_BASE (IO_MEM_ARM9_ARM11 + 0x61000) - #define I2C2_REGS_BASE (IO_MEM_ARM9_ARM11 + 0x44000) - #define I2C3_REGS_BASE (IO_MEM_ARM9_ARM11 + 0x48000) typedef struct { - vu8 REG_I2C_DATA; - vu8 REG_I2C_CNT; - vu16 REG_I2C_CNTEX; - vu16 REG_I2C_SCL; + vu8 I2C_DATA; + vu8 I2C_CNT; + vu16 I2C_CNTEX; + vu16 I2C_SCL; } I2cRegs; +enum +{ + I2C_BUS1 = 0, + I2C_BUS2 = 1, + I2C_BUS3 = 2 +}; + static const struct { u8 busId; u8 devAddr; } i2cDevTable[] = { - {0, 0x4A}, - {0, 0x7A}, - {0, 0x78}, - {1, 0x4A}, - {1, 0x78}, - {1, 0x2C}, - {1, 0x2E}, - {1, 0x40}, - {1, 0x44}, - {2, 0xA6}, // TODO: Find out if 0xA6 or 0xD6 is correct - {2, 0xD0}, - {2, 0xD2}, - {2, 0xA4}, - {2, 0x9A}, - {2, 0xA0}, - {1, 0xEE}, - {0, 0x40}, - {2, 0x54} + {I2C_BUS1, 0x4A}, + {I2C_BUS1, 0x7A}, + {I2C_BUS1, 0x78}, + {I2C_BUS2, 0x4A}, + {I2C_BUS2, 0x78}, + {I2C_BUS2, 0x2C}, + {I2C_BUS2, 0x2E}, + {I2C_BUS2, 0x40}, + {I2C_BUS2, 0x44}, + {I2C_BUS3, 0xA6}, // TODO: Find out if 0xA6 or 0xD6 is correct + {I2C_BUS3, 0xD0}, + {I2C_BUS3, 0xD2}, + {I2C_BUS3, 0xA4}, + {I2C_BUS3, 0x9A}, + {I2C_BUS3, 0xA0}, + {I2C_BUS2, 0xEE}, + {I2C_BUS1, 0x40}, + {I2C_BUS3, 0x54} }; -static void i2cWaitBusy(I2cRegs *const regs) -{ - while(regs->REG_I2C_CNT & I2C_ENABLE); -} - static I2cRegs* i2cGetBusRegsBase(u8 busId) { I2cRegs *base; switch(busId) { - case 0: + case I2C_BUS1: base = (I2cRegs*)I2C1_REGS_BASE; break; - case 1: + case I2C_BUS2: base = (I2cRegs*)I2C2_REGS_BASE; break; - case 2: + case I2C_BUS3: base = (I2cRegs*)I2C3_REGS_BASE; break; default: @@ -91,147 +91,143 @@ return base; } -void I2C_init(void) +static void i2cWaitBusyIrq(const I2cRegs *const regs) { - static bool initialized; - - /* run-once */ - if(initialized) - return; - - I2cRegs *regs = i2cGetBusRegsBase(0); // Bus 1 - i2cWaitBusy(regs); - regs->REG_I2C_CNTEX = 2; // ? - regs->REG_I2C_SCL = 1280; // ? - - regs = i2cGetBusRegsBase(1); // Bus 2 - i2cWaitBusy(regs); - regs->REG_I2C_CNTEX = 2; // ? - regs->REG_I2C_SCL = 1280; // ? - - regs = i2cGetBusRegsBase(2); // Bus 3 - i2cWaitBusy(regs); - regs->REG_I2C_CNTEX = 2; // ? - regs->REG_I2C_SCL = 1280; // ? - - initialized = true; + while(regs->I2C_CNT & I2C_ENABLE) __wfi(); } -static bool i2cStartTransfer(I2cDevice devId, u8 regAddr, bool read, I2cRegs *const regs) +void I2C_init(void) { - const u8 devAddr = i2cDevTable[devId].devAddr; + static bool initialized = false; + + /* run-once */ + if(initialized) return; + initialized = true; + IRQ_registerHandler(IRQ_I2C1, 14, 0, true, NULL); + IRQ_registerHandler(IRQ_I2C2, 14, 0, true, NULL); + IRQ_registerHandler(IRQ_I2C3, 14, 0, true, NULL); - u32 i = 0; - for(; i < 8; i++) + I2cRegs *regs = i2cGetBusRegsBase(I2C_BUS1); + while(regs->I2C_CNT & I2C_ENABLE); + regs->I2C_CNTEX = 2; // TODO: Find out what this does. If bit 1 is not set I2C hangs. + regs->I2C_SCL = 1280; // TODO: How to calculate the frequency. + + regs = i2cGetBusRegsBase(I2C_BUS2); + while(regs->I2C_CNT & I2C_ENABLE); + regs->I2C_CNTEX = 2; + regs->I2C_SCL = 1280; + + regs = i2cGetBusRegsBase(I2C_BUS3); + while(regs->I2C_CNT & I2C_ENABLE); + regs->I2C_CNTEX = 2; + regs->I2C_SCL = 1280; +} + +static bool i2cStartTransfer(u8 devAddr, u8 regAddr, bool read, I2cRegs *const regs) +{ + u32 tries = 8; + do { - i2cWaitBusy(regs); + // This is a special case where we can't predict when or if + // the IRQ has already fired. If it fires after checking but + // before a wfi this would hang. + while(regs->I2C_CNT & I2C_ENABLE) __wfe(); // Select device and start. - regs->REG_I2C_DATA = devAddr; - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_START; - i2cWaitBusy(regs); - if(!I2C_GET_ACK(regs->REG_I2C_CNT)) // If ack flag is 0 it failed. + regs->I2C_DATA = devAddr; + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_WRITE | I2C_START; + i2cWaitBusyIrq(regs); + if(!(regs->I2C_CNT & I2C_ACK)) // If ack flag is 0 it failed. { - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; continue; } - // Select register and change direction to write. - regs->REG_I2C_DATA = regAddr; - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_WRITE; - i2cWaitBusy(regs); - if(!I2C_GET_ACK(regs->REG_I2C_CNT)) // If ack flag is 0 it failed. + // Select register. + regs->I2C_DATA = regAddr; + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_WRITE; + i2cWaitBusyIrq(regs); + if(!(regs->I2C_CNT & I2C_ACK)) { - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; continue; } // Select device in read mode for read transfer. if(read) { - regs->REG_I2C_DATA = devAddr | 1u; // Set bit 0 for read. - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_START; - i2cWaitBusy(regs); - if(!I2C_GET_ACK(regs->REG_I2C_CNT)) // If ack flag is 0 it failed. + regs->I2C_DATA = devAddr | 1u; // Set bit 0 for read. + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_WRITE | I2C_START; + i2cWaitBusyIrq(regs); + if(!(regs->I2C_CNT & I2C_ACK)) { - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; continue; } } break; - } + } while(--tries > 0); - if(i < 8) return true; - else return false; + return tries > 0; } bool I2C_readRegBuf(I2cDevice devId, u8 regAddr, u8 *out, u32 size) { - const u32 oldState = enterCriticalSection(); // TODO: Don't block interrupts. const u8 busId = i2cDevTable[devId].busId; + const u8 devAddr = i2cDevTable[devId].devAddr; I2cRegs *const regs = i2cGetBusRegsBase(busId); - if(!i2cStartTransfer(devId, regAddr, true, regs)) - { - leaveCriticalSection(oldState); - return false; - } + if(!i2cStartTransfer(devAddr, regAddr, true, regs)) return false; while(--size) { - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_READ | I2C_ACK; - i2cWaitBusy(regs); - *out++ = regs->REG_I2C_DATA; + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_READ | I2C_ACK; + i2cWaitBusyIrq(regs); + *out++ = regs->I2C_DATA; } - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_READ | I2C_STOP; - i2cWaitBusy(regs); - *out = regs->REG_I2C_DATA; // Last byte + // Last byte transfer. + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_READ | I2C_STOP; + i2cWaitBusyIrq(regs); + *out = regs->I2C_DATA; - leaveCriticalSection(oldState); return true; } bool I2C_writeRegBuf(I2cDevice devId, u8 regAddr, const u8 *in, u32 size) { - const u32 oldState = enterCriticalSection(); // TODO: Don't block interrupts. const u8 busId = i2cDevTable[devId].busId; + const u8 devAddr = i2cDevTable[devId].devAddr; I2cRegs *const regs = i2cGetBusRegsBase(busId); - if(!i2cStartTransfer(devId, regAddr, false, regs)) - { - leaveCriticalSection(oldState); - return false; - } + if(!i2cStartTransfer(devAddr, regAddr, false, regs)) return false; while(--size) { - regs->REG_I2C_DATA = *in++; - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_WRITE; - i2cWaitBusy(regs); - if(!I2C_GET_ACK(regs->REG_I2C_CNT)) // If ack flag is 0 it failed. + regs->I2C_DATA = *in++; + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_WRITE; + i2cWaitBusyIrq(regs); + if(!(regs->I2C_CNT & I2C_ACK)) { - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; - leaveCriticalSection(oldState); + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; return false; } } - regs->REG_I2C_DATA = *in; - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_WRITE | I2C_STOP; - i2cWaitBusy(regs); - if(!I2C_GET_ACK(regs->REG_I2C_CNT)) // If ack flag is 0 it failed. + // Last byte transfer. + regs->I2C_DATA = *in; + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_DIRE_WRITE | I2C_STOP; + i2cWaitBusyIrq(regs); + if(!(regs->I2C_CNT & I2C_ACK)) { - regs->REG_I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; - leaveCriticalSection(oldState); + regs->I2C_CNT = I2C_ENABLE | I2C_IRQ_ENABLE | I2C_ERROR | I2C_STOP; return false; } - leaveCriticalSection(oldState); return true; } diff --git a/source/arm11/hardware/interrupt.c b/source/arm11/hardware/interrupt.c index 0e2e8ba..a55a2a6 100644 --- a/source/arm11/hardware/interrupt.c +++ b/source/arm11/hardware/interrupt.c @@ -22,51 +22,47 @@ #include "arm11/hardware/cfg11.h" -IrqHandler irqHandlerTable[224] = {0}; // First 32 interrupts are private to each core (4 * 32). - // 96 external interrupts (total 128). +// First 32 interrupts are private to each core (4 * 32). +// 96 external interrupts (total 128). +IrqHandler irqHandlerTable[224] = {0}; void IRQ_init(void) { - // Disable the interrupt interface for this CPU - REG_CPU_II_CNT = 0; + REG_CPU_II_CNT = 0; // Disable the interrupt interface for this CPU. - - if(!__getCpuId()) + if(!__getCpuId()) // Core 0 { - // Disable FIQs - REG_CFG11_FIQ_CNT = 1; + REG_CFG11_FIQ_CNT = 1; // Disable FIQs. - // Disable the global interrupt distributor - REG_GID_CNT = 0; + REG_GID_CNT = 0; // Disable the global interrupt distributor. - // Disable all 128 interrupts - REGs_GID_ENA_CLR[0] = 0xFFFFFFFFu; // Interrupts 0-15 cant be disabled + // Disable all 128 interrupts. + REGs_GID_ENA_CLR[0] = 0xFFFFFFFFu; // Interrupts 0-15 cant be disabled. REGs_GID_ENA_CLR[1] = 0xFFFFFFFFu; REGs_GID_ENA_CLR[2] = 0xFFFFFFFFu; REGs_GID_ENA_CLR[3] = 0xFFFFFFFFu; - // Set all pending interrupts to inactive state - REGs_GID_PEN_CLR[0] = 0xFFFFFFFFu; // Interrupt 0-15 can't be set to inactive apparently + // Set all pending interrupts to inactive state. + REGs_GID_PEN_CLR[0] = 0xFFFFFFFFu; // Interrupt 0-15 can't be set to inactive apparently. REGs_GID_PEN_CLR[1] = 0xFFFFFFFFu; REGs_GID_PEN_CLR[2] = 0xFFFFFFFFu; REGs_GID_PEN_CLR[3] = 0xFFFFFFFFu; - // Set all 128 interrupts to lowest priority + // Set all 128 interrupts to lowest priority. for(u32 i = 0; i < 32; i++) REGs_GID_IPRIO[i] = 0xE0E0E0E0u; // Set all 128 interrupts to target no CPU. - // Interrupt 0-31 can't be changed + // Interrupt 0-31 can't be changed. for(u32 i = 8; i < 32; i++) REGs_GID_ITARG[i] = 0; - // Set all interrupts to rising edge sensitive and 1-N software model + // Set all interrupts to rising edge sensitive and 1-N software model. for(u32 i = 0; i < 8; i++) REGs_GID_ICONF[i] = 0xFFFFFFFFu; - // Enable the global interrupt distributor - REG_GID_CNT = 1; + REG_GID_CNT = 1; // Enable the global interrupt distributor. } - else + else // Other core. Same as above but for core specific IRQs. { REGs_GID_PEN_CLR[0] = 0xFFFFFFFFu; @@ -77,14 +73,11 @@ } - // Mask no interrupt - REG_CPU_II_MASK = 0xF0; - // All priority bits are compared for pre-emption - REG_CPU_II_BIN_POI = 3; - // Enable the interrupt interface for this CPU - REG_CPU_II_CNT = 1; + REG_CPU_II_MASK = 0xF0; // Mask no interrupt. + REG_CPU_II_BIN_POI = 3; // All priority bits are compared for pre-emption. + REG_CPU_II_CNT = 1; // Enable the interrupt interface for this CPU. - // Get rid of all interrupts stuck in pending/active state + // Get rid of all interrupts stuck in pending/active state. u32 tmp; do { @@ -100,20 +93,24 @@ const u32 oldState = enterCriticalSection(); - if(handler) irqHandlerTable[(id < 32 ? 32 * cpuId + id : 96u + id)] = handler; + irqHandlerTable[(id < 32 ? 32 * cpuId + id : 96u + id)] = handler; + // Priority u32 shift = (id % 4 * 8) + 4; u32 tmp = REGs_GID_IPRIO[id>>2] & ~(0xFu<>2] = tmp | (u32)prio<>2] & ~(0xFu<>2] = tmp | (u32)cpuMask<>4] & ~(1u<>4] = tmp | (u32)edgeTriggered<>5] = 1u<<(id % 32); leaveCriticalSection(oldState); @@ -144,7 +141,7 @@ { const u32 oldState = enterCriticalSection(); - u32 shift = (id % 4 * 8) + 4; + const u32 shift = (id % 4 * 8) + 4; u32 tmp = REGs_GID_IPRIO[id>>2] & ~(0xFu<>2] = tmp | (u32)prio<