diff --git a/source/arm11/start.s b/source/arm11/start.s
index 153f29d..a8ddf28 100644
--- a/source/arm11/start.s
+++ b/source/arm11/start.s
@@ -94,14 +94,12 @@
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register
 	mov r0, #0
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
-
 	mcr p15, 0, r0, c7, c7, 0   @ Invalidate Both Caches. Also flushes the branch target cache
 	mcr p15, 0, r0, c7, c10, 4  @ Data Synchronization Barrier
 	mcr p15, 0, r0, c7, c5, 4   @ Flush Prefetch Buffer
 
 	mrc p15, 0, r4, c0, c0, 5   @ Get CPU ID
 	ands r4, r4, #3
-
 	bleq stubExceptionVectors   @ Stub the vectors in AXIWRAM bootrom vectors jump to
 
 	mov sp, #0                  @ SVC mode sp (unused, aborts)
@@ -125,12 +123,10 @@
 	ldr r1, =__bss_end__
 	sub r1, r1, r0
 	bl clearMem
-
 	@ Setup newlib heap
 	ldr r0, =A11_HEAP_END
 	ldr r1, =fake_heap_end
 	str r0, [r1]
-
 	blx __libc_init_array       @ Initialize ctors and dtors
 
 	@ Wakeup core 1.
@@ -141,7 +137,6 @@
 	mov r3, #1<<17
 	orr r3, r3, #1
 	str r3, [r1]
-
 _start_skip_bss_init_array:
 	ldr r2, =0xFFFF70F
 	mcr p15, 0, r2, c15, c12, 0 @ Write Performance Monitor Control Register
@@ -218,8 +213,8 @@
 
 deinitCpu:
 	mov r3, lr
-	cpsid aif, #31              @ System mode
 
+	cpsid aif, #31              @ System mode
 	bl stubExceptionVectors
 	bl flushDCache
 	mov r2, #0
@@ -238,10 +233,9 @@
 	                            @ Instruction folding, SMP mode: the CPU is taking part in coherency
 	                            @ and L1 parity checking
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
-
-	mcr p15, 0, r2, c7, c7, 0  @ Invalidate Both Caches. Also flushes the branch target cache
-	mcr p15, 0, r2, c7, c10, 4 @ Data Synchronization Barrier
-	mcr p15, 0, r2, c7, c5, 4  @ Flush Prefetch Buffer
+	mcr p15, 0, r2, c7, c7, 0   @ Invalidate Both Caches. Also flushes the branch target cache
+	mcr p15, 0, r2, c7, c10, 4  @ Data Synchronization Barrier
+	mcr p15, 0, r2, c7, c5, 4   @ Flush Prefetch Buffer
 	bx r3
 
 
diff --git a/source/arm9/firmwriter.c b/source/arm9/firmwriter.c
index 5307e0e..d78608e 100644
--- a/source/arm9/firmwriter.c
+++ b/source/arm9/firmwriter.c
@@ -134,7 +134,7 @@
 #endif
 
 	// verify fastboot magic
-	if(memcmp((void*)updateBuffer + 0x200, "FASTBOOT 3DS   ", 16) != 0)
+	if(memcmp((void*)updateBuffer + 0x200, "fastboot3DS    ", 16) != 0)
 		return -4;
 
 	// Check version
@@ -155,7 +155,7 @@
 	}
 
 	// verify fastboot is installed to firm0:/
-	if(memcmp(firm0Buf, "FASTBOOT 3DS   ", 16) != 0)
+	if(memcmp(firm0Buf, "fastboot3DS    ", 16) != 0)
 	{
 		free(firm0Buf);
 		return UPDATE_ERR_NOT_INSTALLED;
diff --git a/source/arm9/hardware/exception.s b/source/arm9/hardware/exception.s
index cd84830..02f9dda 100644
--- a/source/arm9/hardware/exception.s
+++ b/source/arm9/hardware/exception.s
@@ -88,7 +88,7 @@
 	ldr lr, [sp], #4
 	msr cpsr_c, #0xD2                @ IRQ mode, IRQ disabled
 	ldr r0, [sp], #4
-	msr spsr_fsxc, r0
+	msr spsr_cxsf, r0
 irqHandler_skip_processing:
 	ldmfd sp!, {r0-r3, r12, pc}^
 
diff --git a/source/arm9/start.s b/source/arm9/start.s
index c13c529..7bd961e 100644
--- a/source/arm9/start.s
+++ b/source/arm9/start.s
@@ -52,11 +52,11 @@
 
 
 __start__:
-	.string "FASTBOOT 3DS   "
+	.string "fastboot3DS    "
 	.word   (VERS_MAJOR<<16 | VERS_MINOR)
 
 _start:
-	msr cpsr_fsxc, #0xD3         @ Disable all interrupts, SVC mode
+	msr cpsr_cxsf, #0xD3         @ Disable all interrupts, SVC mode
 
 	@ Control register:
 	@ [19] ITCM load mode         : disabled
@@ -72,7 +72,6 @@
 	@ [0]  MPU                    : disabled
 	ldr r0, =0x2078
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register
-
 	mov r0, #0
 	mcr p15, 0, r0, c7, c5, 0   @ Invalidate I-Cache
 	mcr p15, 0, r0, c7, c6, 0   @ Invalidate D-Cache
@@ -82,13 +81,13 @@
 	bl setupTcms                @ Setup and enable DTCM and ITCM
 
 	mov sp, #0                  @ SVC mode sp (Unused, aborts)
-	msr cpsr_fsxc, #0xD7        @ Abort mode
+	msr cpsr_cxsf, #0xD7        @ Abort mode
 	mov sp, #A9_EXC_STACK_END
-	msr cpsr_fsxc, #0xDB        @ Undefined mode
+	msr cpsr_cxsf, #0xDB        @ Undefined mode
 	mov sp, #A9_EXC_STACK_END
-	msr cpsr_fsxc, #0xD2        @ IRQ mode
+	msr cpsr_cxsf, #0xD2        @ IRQ mode
 	ldr sp, =A9_IRQ_STACK_END
-	msr cpsr_fsxc, #0xDF        @ System mode
+	msr cpsr_cxsf, #0xDF        @ System mode
 	ldr sp, =A9_STACK_END
 
 	bl setupMpu
@@ -98,12 +97,10 @@
 	ldr r1, =__bss_end__
 	sub r1, r1, r0
 	bl clearMem
-
 	@ Setup newlib heap
 	mov r0, #A9_HEAP_END
 	ldr r1, =fake_heap_end
 	str r0, [r1]
-
 	blx __libc_init_array       @ Initialize ctors and dtors
 
 	mov r0, #0                  @ argc
@@ -111,8 +108,7 @@
 	blx main
 	_start_lp:
 		mov r0, #0
-		@ Wait for interrupt
-		mcr p15, 0, r0, c7, c0, 4
+		mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
 		b _start_lp
 
 
@@ -146,7 +142,6 @@
 	mov r1, #(ITCM_BASE | 0x24) @ Base = 0x00000000, size = 512 KB (32 KB mirrored)
 	mcr p15, 0, r0, c9, c1, 0   @ Write DTCM region reg
 	mcr p15, 0, r1, c9, c1, 1   @ Write ITCM region reg
-
 	mrc p15, 0, r0, c1, c0, 0   @ Read control register
 	orr r0, r0, #0x50000        @ Enable DTCM and ITCM
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register
@@ -320,8 +315,8 @@
 
 deinitCpu:
 	mov r3, lr
-	msr cpsr_fsxc, #0xDF        @ System mode
 
+	msr cpsr_cxsf, #0xDF        @ System mode
 	@ Stub vectors to endless loops
 	mov r0, #A9_RAM_BASE
 	mov r1, #6
@@ -337,7 +332,6 @@
 	ldr r1, =0x1005             @ MPU, D-Cache and I-Cache bitmask
 	bic r0, r0, r1              @ Disable MPU, D-Cache and I-Cache
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register
-
 	mcr p15, 0, r2, c7, c5, 0   @ Invalidate I-Cache
 	mcr p15, 0, r2, c7, c6, 0   @ Invalidate D-Cache
 	mcr p15, 0, r2, c7, c10, 4  @ Drain write buffer