diff --git a/source/arm11/cpu.s b/source/arm11/cpu.s
index d776c4a..47e0c8a 100644
--- a/source/arm11/cpu.s
+++ b/source/arm11/cpu.s
@@ -72,11 +72,11 @@
 
 setupVfp:
 	mov r0, #0
-	mov r1, #0x00F00000         @ Give full access to cp10/11 in user and privileged mode
+	mov r1, #0xF00000           @ Give full access to cp10/11 in user and privileged mode
 	mcr p15, 0, r1, c1, c0, 2   @ Write Coprocessor Access Control Register
 	mcr p15, 0, r0, c7, c5, 4   @ Flush Prefetch Buffer
 	mov r1, #0x40000000         @ Clear exception bits and enable VFP11
-	mov r2, #0x03C00000         @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode
+	mov r2, #0x3C00000          @ Round towards zero (RZ) mode, flush-to-zero mode, default NaN mode
 	fmxr fpexc, r1              @ Write Floating-point exception register
 	fmxr fpscr, r2              @ Write Floating-Point Status and Control Register
 	bx lr
@@ -97,9 +97,9 @@
 	bic r0, r0, r1
 	mcr p15, 0, r0, c1, c0, 0   @ Write control register
 	mrc p15, 0, r0, c1, c0, 1   @ Read Auxiliary Control Register
-	bic r0, r0, #0x7F           @ Return stack, Dynamic branch prediction, Static branch prediction,
-                                @ Instruction folding, L1 and L2 caches are exclusive,
-                                @ SMP mode: the CPU is taking part in coherency and L1 parity checking
+	bic r0, r0, #0x6F           @ Return stack, Dynamic branch prediction, Static branch prediction,
+                                @ Instruction folding, SMP mode: the CPU is taking part in coherency
+                                @ and L1 parity checking
 	mcr p15, 0, r0, c1, c0, 1   @ Write Auxiliary Control Register
 
 	mcr p15, 0, r2, c7, c5, 4   @ Flush Prefetch Buffer
diff --git a/source/arm11/mmu.c b/source/arm11/mmu.c
index 85fb60f..33e0213 100644
--- a/source/arm11/mmu.c
+++ b/source/arm11/mmu.c
@@ -34,6 +34,7 @@
 
 
 extern void clearMem(u32 *adr, u32 size);
+extern u32 __start__;
 
 /**
  * @brief      Maps up to 4096 1 MB sections of memory.
@@ -120,7 +121,7 @@
 				L1_TO_L2(MAKE_CUSTOM_NORM_ATTR(POLICY_WRITE_BACK_ALLOC_BUFFERED, POLICY_WRITE_BACK_ALLOC_BUFFERED)));
 
 	// Map boot11 mirror to loader executable start (exception vectors)
-	mmuMapPages(BOOT11_MIRROR2, AXIWRAM_BASE + 0x5000u, 1, (u32*)(A11_MMU_TABLES_BASE + 0x4800u), true,
+	mmuMapPages(BOOT11_MIRROR2, (u32)&__start__, 1, (u32*)(A11_MMU_TABLES_BASE + 0x4800u), true,
 				PERM_PRIV_RO_USR_NO_ACC, 1, false,
 				L1_TO_L2(MAKE_CUSTOM_NORM_ATTR(POLICY_WRITE_BACK_ALLOC_BUFFERED, POLICY_WRITE_BACK_ALLOC_BUFFERED)));
 
@@ -140,9 +141,9 @@
 	u32 tmp;
 	// Modify Auxiliary Control Register
 	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r" (tmp) : );
-	tmp |= 0x7Fu;     // Enable Return stack, Dynamic branch prediction, Static branch prediction,
-	                  // Instruction folding, L1 and L2 caches are exclusive,
-	                  // SMP mode: the CPU is taking part in coherency and L1 parity checking
+	tmp |= 0x6Fu;     // Enable Return stack, Dynamic branch prediction, Static branch prediction,
+	                  // Instruction folding, SMP mode: the CPU is taking part in coherency
+	                  // and L1 parity checking
 	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r" (tmp));
 
 	// Modify Control Register